Structure of circuit board and method for fabricating same

Abstract

An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully comprehended by reading the detailed description of the preferred embodiment listed below, with reference to the accompanying drawings, wherein:

FIG. 1 (PRIOR ART) is a schematic cross-sectional diagram showing a conventional package with a semiconductor chip embedded therein; and

FIGS. 2A-2I are schematic cross-sectional diagrams showing the method in accordance with an embodiment of the present invention.

Claims

1. A method of fabricating a structure with semiconductor chips embedded therein, comprising: providing a carrier board having a first surface and an opposing second surface, therewith forming a plurality of both through openings in the carrier board, and first trenches on the first surface thereof surrounding the through openings without penetrating the carrier board;providing a first dielectric layer, and putting the first surface of the carrier board on the first dielectric layer;providing a semiconductor chip, which has an active surface and an opposing inactive surface, therewith disposing the semiconductor chip within each of the through openings of the carrier board, whose inactive surface likewise is on the dielectric layer, and then pressing to bond together the carrier board, the semiconductor chip, and the first dielectric layer, so that the first dielectric layer fills the first trenches and the gap between the semiconductor chip and the carrier board; and forming second trenches on the second surface of the carrier board at the positions corresponding to the first trenches, thereby interconnecting mutually to form through trenches in the carrier board.

2. The method of claim 1, wherein the first dielectric layer further comprises a metal film formed on one surface thereof, which is not in contact with the carrier board.

3. The method of claim 1, further comprising: forming a second dielectric layer on the second surface of the carrier board and on the active surface of the semiconductor chip, so that the second dielectric layer fills the second trenches; andforming a plurality of conductive vias in the second dielectric layer, as well as forming a circuit layer on the second dielectric layer, wherein the conductive vias electrically connect to the active surface of the semiconductor chip.

4. The method of claim 3, further comprising forming a built-up structure on the second dielectric layer and on the circuit layer, wherein the built-up structure includes: at least a dielectric layer, at least a built-up circuit layer, a plurality of connecting pads, and a plurality of conductive vias, to thereby electrically connect to the circuit layer on the second dielectric layer.

5. The method of claim 3, wherein at the same time as forming the circuit layer on the second dielectric layer, a metal layer is formed on the outer surface of the first dielectric layer.

6. The method of claim 4, wherein at the same time as forming the built-up circuit layer, a metal layer is successively stacked on the outer surface of the first dielectric layer so as to form a metallic board with a multi-layer structure.

7. The method of claim 6, further comprising forming openings in the metallic board at the positions corresponding to the through trenches.

8. The method of claim 7, further comprising using the through trenches in the carrier board for a cutting process to form a package structure with the semiconductor chip embedded and the circuit layer integrated therein, wherein some residual of the first dielectric layer is present around the periphery of the package.

9. The method of claim 1, wherein the carrier board is one of a heat sink made of metal, an insulating board, and a circuit board.

10. A structure with semiconductor chips embedded therein, comprising: a carrier board having a first surface and an opposing second surface, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings formed in the same;a plurality of semiconductor chips having an active surface and an opposing inactive surface each, received in the through openings of the carrier board; anda first dielectric layer formed on the first surface of the carrier board, and filling the gap between the semiconductor chip and the carrier and parts of the through trenches.

11. The structure of claim 10, further comprising: a second dielectric layer formed on the second surface of the carrier board and on the active surface of the semiconductor chip, also filling the residual spaces of the through trenches; and a circuit layer formed on the second dielectric layer, together with a plurality of conductive vias formed in the same, to thereby electrically connect to the active surface of the semiconductor chip.

12. The structure of claim 11, further comprising a built-up structure on the second dielectric layer and on the circuit layer, wherein the built-up structure includes: at least a dielectric layer, at least a built-up circuit layer, a plurality of connecting pads, and a plurality of conductive vias, to thereby electrically connect to the circuit layer on the second dielectric layer.

13. The structure of claim 10, further comprising a metallic board formed on the outer surface of the first dielectric layer.

14. The structure of claim 13, further comprising openings formed in the metallic board at the positions corresponding to the through trenches.

15. The structure of claim 10, wherein the carrier board is one of a heat sink made of metal, an insulating board, and a circuit board.

16. A structure with a semiconductor chip embedded therein, comprising: a carrier board having a first surface and an opposing second surface, therewith a through opening formed in the carrier board;a semiconductor chip having an active surface and an opposing inactive surface, received in the through opening of the carrier board;a first dielectric layer formed on the first surface of the carrier board, and some residual of the first dielectric layer is present around the periphery of the carrier board; anda second dielectric layer formed on the second surface of the carrier board and on the active surface of the semiconductor chip.

17. The structure of claim 16, further comprising a circuit layer formed on the second dielectric layer, together with a plurality of conductive vias formed in the same, to thereby electrically connect to the active surface of the semiconductor chip.

18. The structure of claim 17, further comprising a built-up structure on the second dielectric layer and on the circuit layer, wherein the built-up structure includes: at least a dielectric layer, at least a built-up circuit layer, a plurality of connecting pads, and a plurality of conductive vias, to thereby electrically connect to the circuit layer on the second dielectric layer.

19. The structure of claim 16, further comprising a metallic board formed on the outer surface of the first dielectric layer.

20. The structure of claim 16, wherein the carrier board is one of a heat sink made of metal, an insulating board, and a circuit board.