Substrate of chip package and chip package structure thereof

Abstract

A substrate of chip package and the chip package structure thereof centralizes the bonding area under a chip carrier area and protrudes the bonding area from the chip carrier area to a chip package so as to increase the reliability of bump type surface mount technology during the second-level electronic assembly. Furthermore, the carrier for produce the substrate is recyclable during the chip package procedure so as to reduce the production cost.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross-sectional diagram of a conventional chip package structure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D are cross-sectional diagrams of the substrate in accordance with an embodiment of the present invention;

FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D are cross-sectional diagrams of the substrate in accordance with another embodiment of the present invention;

FIG. 4 is a cross-sectional diagram of the chip package structure in accordance with FIG. 3A;

FIG. 5 is a cross-sectional diagram of the CMOS sensor chip package in accordance with FIG. 3A;

FIG. 6, FIG. 7, and FIG. 8 are cross-sectional diagrams of the flip chip package structure in accordance with FIG. 3B; and

FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, and FIG. 9E are cross-sectional diagrams of the chip package of the package procedure in accordance with an embodiment of the present invention.

Claims

1. A substrate of a chip package, comprising: a plurality of connection pads separated from each other with an interval;an insulation layer, wherein a lower surface of said insulation layer contacts but exposes part of an upper surface of said connection pads to form at least one cavity; anda conductive solder pad arranged on said exposed upper surface of said connection pads, wherein an area of said upper surface of said insulation layer between said conductive solder pad is defined as a chip carrier area, wherein said interval between connection pads is smaller than a size of said chip carrier area.

2. A substrate of a chip package according to claim 1, further comprising a die paddle configured between said connection pads, wherein the size of said die paddle is smaller than the size of a chip.

3. A substrate of a chip package according to claim 2, wherein said insulation layer exposes an upper surface of said die paddle.

4. A substrate of a chip package according to claim 1, further comprising a metal layer configured on a lower surface of said connection pads.

5. A substrate of a chip package according to claim 1, wherein said connection pads are metal leads.

6. A chip package structure, comprising: a plurality of connection pads separated from each other with an interval;an insulation layer, wherein said insulation layer comprises a lower surface contacts with an upper surface of said connection pads and expose part of said upper surface of said connection pads, wherein said insulation layer and said connection pads form at least one cavity;a conductive solder pad arranged on said exposed upper surface of said connection pads, wherein an area of said upper surface of said insulation layer between said conductive solder pad is defined as a chip carrier area, wherein said interval between connection pads is smaller than a size of said chip carrier area;a chip arranged on said chip carrier area;a conductive connection structure electrically connected said chip and said conductive pads; anda molding compound covering said chip and said conductive connection structure.

7. A chip package structure according to claim 6, further comprising a die paddle configured between said connection pads, wherein the size of said die paddle is smaller than the size of said chip.

8. A chip package structure according to claim 7, wherein said insulation layer exposes an upper surface of said die paddle.

9. A chip package structure according to claim 6, further comprising a metal layer configured on a lower surface of said connection pads.

10. A chip package structure according to claim 6, wherein said connection pads are metal leads.

11. A chip package structure according to claim 6, further comprising an adhesive layer configured between said chip and said insulation layer.

12. A chip package structure according to claim 6, wherein said molding compound exposes an upper surface of said chip.

13. A chip package structure according to claim 12, further comprising an adhesive layer on said molding compound, and an upper substrate arranged on said adhesive layer and positioned on said upper surface of said chip.

14. A chip package structure according to claim 6, wherein said conductive connection structure is a conductive wire.

15. A chip package structure according to claim 6, wherein said conductive connection structure is a golden bump.

16. A chip package structure according to claim 6, wherein said conductive connection structure is a solder ball.