Patent Application
20250087632
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components, hence more functions, to be integrated into a given area. When creating semiconductor packages having a top die and a bottom die, the top die may need to be electrically connected to the bottom die. Formation of power through silicon vias (TSV) may need more processing steps, may occupy more area, and may increase cost in making CPU top die. It is high desirable to reduce the area and cost and improve the form factor.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
According to various embodiments, two semiconductor dies, one attached on top of the other may be electrically connected to each other. In some embodiments, a first semiconductor die that includes a central processing unit (CPU) or includes a graphic processing unit (GPU) is attached, e.g., is bonded, over a second semiconductor die that includes a random-access memory (RAM) circuit and/or a static RAM (SRAM) circuit. In some embodiments, one or more TSVs or a TSV tower for transferring power, e.g., power TSVs, are arranged outside the semiconductor die having the CPU.
The power may be regulated by an integrated voltage regulator (IVR) that is attached to a power rail structure, e.g., a power rail or a super power rail (SPR), that is inside the semiconductor die. The IVR may receive the power from a power source unit (PSU) and provide a regulated power, e.g., regulated voltage and current, to one or more semiconductor dies that may include the semiconductor die that has the CPU/GPU. In some embodiments, the IVR is connected by one or more vias that extend through a dielectric layer, e.g., an insulating or encapsulant layer, outside the semiconductor die that includes the CPU/GPU. Thus, each via of the one or more vias is a through dielectric via (TDV) that is connected between the IVR and another semiconductor die, e.g., the semiconductor die that includes the SRAM and, thus, the power is provided by the TDV to the other semiconductor die. Implementing the one or more TDVs that is arranged outside the semiconductor die that has the CPU/GPU, may reduce the processing steps and cost of packaging and also may improve the form factor.
As shown, each one of the semiconductor dies 111 and 113 include a backside interconnect structure 112 at the top and a front-side interconnect structure 107 at the bottom. The backside interconnect structure 112 may include a power rail structure for power delivery in the semiconductor dies 111 and 113. In some embodiments, each one of the semiconductor dies 111 and 113 include a semiconductor device layer 105, which may include active devices (e.g., transistors) that are interconnected together by the backside interconnect structure 112 to provide functional circuitry. For example, each one of the semiconductor dies 111 and 113 may provide logic circuitry (e.g., a central processing unit (CPU), a graphic processing unit (GPU), or the like) in the completed semiconductor package. The semiconductor die 115 includes a front-side interconnect structure 103 at the top such that the face-to-face bonding is connected between the front-side interconnect structure 103 of the semiconductor die 115 and the front-side interconnect structure 107 of the semiconductor dies 111 and 113. In some embodiments, the package 160 has one of the semiconductor die 111 or the semiconductor die 113. Alternatively, the package 160 may include additional semiconductor dies at a same level as the semiconductor dies 111 and 113.
Further, each one of the semiconductor dies 111 and 113 includes an insulating bonding layer 109 on the front-side interconnect structure 107, and bond pads 117 that are formed in an insulating bonding layer 109. The bond pads 117 may be conductive pillars, pads, or the like, to which external connections are made. The bond pads 117 can be formed of a metal, such as copper, aluminum, or the like, and can be formed by, for example, by plating, or the like. In some embodiments, the bond pads 117 may be electrically connected to conductive features of the front-side interconnect structure 107 by conductive vias (sometimes referred to as bond pad vias). The insulating bonding layer 109 may be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as, silicon oxide, silicon oxynitride, or the like. The insulating bonding layer 109 may be deposited on the front-side interconnect structure 107, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. A planarization process (e.g., a chemical mechanical polish (CMP) or the like) may be performed such that top surfaces of the bond pads 117 and the insulating bonding layer 109 are coplanar (within process variations). As will be described in greater detail below, the planarized bottom surfaces 145 of the semiconductor dies 111 and 113 are bonded to the underlying semiconductor die 115.
The semiconductor die 115 includes a semiconductor device layer 101 and the front-side interconnect structure 103. The semiconductor device layer 101 may include active devices (e.g., transistors) disposed at a top surface of a semiconductor substrate, and the active devices of the semiconductor device layer 101 may be interconnected together by the front-side interconnect structure 103 to provide functional circuitry. For example, each one of the semiconductor dies 111 and 113 may provide memory circuitry (e.g., a static random access memory (SRAM) circuitry, dynamic random access memory (DRAM) circuitry, or the like) in the completed semiconductor package. The semiconductor die 115 further includes an insulating bonding layer 119 on the front-side interconnect structure 103, and bond pads 121 that formed in an insulating bonding layer 119. The bond pads 121 and the insulating bonding layer 119 may be formed of like materials using like processes as the bond pads 117 and the insulating bonding layers 109, respectively, as described above. In some embodiments, a planarization process (e.g., a chemical mechanical polish (CMP) or the like) may be performed such that top surfaces of the bond pads 121 and the insulating bonding layer 119 are coplanar (within process variations).
As shown in
As a result of the bonding, a portion 149 of the semiconductor die 115, e.g., a portion of the front-side interconnect structure 103 of the semiconductor die 115, is not covered by the semiconductor dies 111 and 113 and a subset of the bond pads 121 may be exposed. In some embodiments, the semiconductor die 115 has a width 106, and the semiconductor die 111 has a width 108 that is shorter than the width 106. In some embodiments, the total width of the semiconductor dies 111 and 113 is smaller than the width 106 of the semiconductor die 115. Thus, the portion 149 not covered by the semiconductor dies 111 and 113 has a width 104.
In addition, through vias 120 extend through the height of the insulating layer 114. In embodiments where the insulating layer 114 is made of a dielectric material, the through vias 120 may be referred to as a TDV. As an example to form the through vias 120, openings may be etched through the insulating layer 114 using, for example, a combination of photolithography and etching. The openings may expose certain ones or the bond pads 121. Then, a conductive material (e.g., a metal such as copper or the like) may be filled in the openings to form the through vias 120. Each through via 120 is electrically coupled, e.g., electrically connected, from a first end 131 of the through vias 120 to a bond pad 121 at the top surface 143 of the semiconductor die 115. In addition, a second end 132 of each through via 120 extends to a height of the insulating layer 114, which is the top surface 147.
Next, in
As further illustrated by
In some embodiments, the integrated voltage regulator die 127 provides a constant power, e.g., a constant voltage with the current for each device in the semiconductor die, such as the CPU, the GPU, or the SRAM of the semiconductor dies 111, 113, and 115. The CPU, the GPU, and the SRAM may be sensitive to voltage fluctuation or insufficient current. Thus, for reliable performance, the integrated voltage regulator die 127 is implemented in the semiconductor die that the CPU is located. In some embodiments, the CPU consumes considerable energy of about few tens of watts or even more than a hundred watts when performing calculation intensive tasks. When performing calculation intensive tasks, lack of sufficient current or a voltage drop may reduce CPU clock cycle and damage performance or even shut down the CPU. Thus, the integrated voltage regulator die 127 is used to provide reliable performance by the CPU. In some embodiments, the integrated voltage regulator die 127 generates the reliable voltage when receives a current and voltage from a power source unit and provides the reliable power through the backside interconnect structure 112 to one or more CPU/GPU of the semiconductor dies 111 and 113 and by one or more through vias 120 to SRAM of the semiconductor die 115. In some embodiments, the backside interconnect structure 112 includes a power rail structure. The power rails may be made wider than the connection lines of the die to reduce the ohmic drop when the current is provided for the sensitive devices such as a CPU or a SRAM. The power rail structure is described with respect to
In some embodiments, the regulated power is provided from the integrated voltage regulator die 127 through the backside interconnect structure 112 to the semiconductor dies 111 and 113. Also, the regulated power is provided from the integrated voltage regulator die 127 by the through vias 120 to the semiconductor die 115. In some embodiments, signal communication between the semiconductor dies 111 and 113 and the semiconductor die 115 is done through the bond between the front-side interconnect structure 103 and the front-side interconnect structure 107. Implementing the through vias 120 outside the semiconductor die that has the top semiconductor device, e.g., CPU or GPU, may reduce the processing steps and cost of packaging and also may improve the form factor.
The device layer 204 is formed at the front-side (i.e., the active surface) of the semiconductor substrate 202. The device layer 204 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. In some embodiments, the active devices of the device layer 204 includes Nano-FETs (e.g., nanowire field effect transistors (FETs), Nano-sheet FETs (Nano-FETs), or the like). The Nano-FETs comprise nanostructures 210 (e.g., Nano-sheets, nanowire, or the like) over fins 203 that extend upwards from the base substrate 202, and the nanostructures 210 act as channel regions for the Nano-FETs. The nanostructures 210 may include p-type nanostructures, n-type nanostructures, or a combination thereof.
Gate stacks 212 (including gate dielectric layers 212D and gate electrodes 212E) are disposed over top surfaces of the fins 203 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 210. The gate dielectric layers 212D may be disposed between the gate electrodes 212E and the nanostructures 210. Epitaxial source/drain regions 208 are disposed on the fins 203 on opposing sides of the gate stacks 212, and the nanostructures 210 may extend between adjacent epitaxial source/drain regions 208. Source/drain regions 208 may refer to a source or a drain, individually or collectively dependent upon the context. The device layer 204 may include other types of transistors (e.g., fin field effect transistors (FinFETs) or the like) as well.
An inter-layer dielectric, e.g., an ILD 214, is formed over the front-side of the semiconductor substrate 202. The ILD 214 surrounds and covers the devices of the device layer 204. The ILD 214 may include one or more dielectric layers formed of materials such as silicon oxide, silicon oxynitride, silicon oxycarbonitiride, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. The ILD 214 may be deposited by CVD, ALD, PVD, or the like. In some embodiments, a contact etch stop layer, e.g., a CESL 213, comprising silicon nitride or the like, may be disposed between the ILD 214 and the devices of the device layer 204.
Conductive plugs 216 extend through the ILD 214 and the CESL 213 to electrically and physically couple the devices of the device layer 204. For example, the conductive plugs 216 may couple the gate stacks 212 and source/drain regions 208. In some embodiments, silicide regions may be disposed at the interfaces between the conductive plugs 216 and the source/drain regions 208. The conductive plugs 216 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. Because the conductive plugs 216 are disposed on the front-side of the substrate 202, they may also be referred to as conductive plugs 216, e.g., front-side contacts.
The front-side interconnect structure 206F is disposed over the ILD 214 and conductive plugs 216. The front-side interconnect structure 206F interconnects the devices of the device layer 204 to form integrated circuits. The front-side interconnect structure 206F includes, for example, metallization patterns in one or more dielectric layers. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers with damascene processes, for example. The metallization patterns of the front-side interconnect structure 206F are electrically coupled to the devices of the device layer 204 by the conductive plugs 216.
In
After the first and second bonding layers 218A and 218B are deposited, the carrier substrate 220 may be bonded to the front-side interconnect structure 206F using a suitable technique, such as dielectric-to-dielectric bonding, or the like. The dielectric-to-dielectric bonding process may include applying a surface treatment to one or more of the first bonding layer 218A and the second bonding layer 218B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water or the like) that may be applied to one or more of the first and second bonding layers 218A and 218B. The carrier substrate 220 is then aligned with the front-side interconnect structure 206F and the two are pressed against each other to initiate a pre-bonding of the carrier substrate 220 to the front-side interconnect structure 206F. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). After the pre-bonding, an annealing process may be applied by, for example, heating the front-side interconnect structure 206F and the carrier substrate 220 to a temperature of in a range of 150° C. to 500° C. The annealing process drives triggers the formation of covalent bonds between the first bonding layer 218A and the second bonding layer 218B. After bonding, the first bonding layer 218A and the second bonding layer 218B may be collectively referred to as a bonding layer 218. Other bonding processes, such as ambient bonding, vacuum bonding, or the like may be used in other embodiments.
In
After the substrate 202 and the fins 203 are substantially removed, a backside ILD 226 is deposited on the backside of the device layer 204. The backside ILD 226 may include one or more dielectric layers formed of materials such as silicon oxide, silicon oxynitride, silicon oxycarbonitiride, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. Backside conductive plugs 222 extend through the backside ILD 226 to electrically and physically couple the epitaxial source/drain regions 208. In some embodiments, silicide regions may be disposed at the interfaces between the backside conductive plugs 222 and the source/drain regions 208. The backside conductive plugs 222 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. The backside conductive plugs 222 allow for additional connections to be made to a backside of the device layer 204 for increased routing flexibility.
A backside interconnect structure 206B is formed over the backside ILD 226 and backside conductive plugs 222 on the backside of the device layer 204. The backside interconnect structure 206B may include, for example, metallization patterns in one or more dielectric layers. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers with damascene processes, for example. Specifically, the backside interconnect structure 206B may provide power delivery circuits to the devices of the device layer 204. For example, the backside interconnect structure 206B may include a power rail 224 (sometimes referred to as a backside power rail, super power rail, power rail structure, or the like) to provide power to the transistors of the device layer 204. Because the power rail 224 may be larger (e.g., wider and/or thicker) than signal lines of the front-side interconnect structure 206F, locating the power rail 224 in the backside interconnect structure 206B improves routing flexibility and allows for additional signal lines to be formed in the front-side interconnect structure 206F.
After the backside interconnect structure 206B is formed, the substrate 202 may be removed (e.g., with a planarization process), to expose the front-side interconnect structure so that an insulating bonding layer/bond pads (e.g., the insulating bonding layer 119 and the bond pads 117 of
The semiconductor package of
At step 620, an insulating layer is deposited over the first semiconductor die and next to the second semiconductor die. As shown in
At step 630, one or more through vias are formed in an insulating layer over the first semiconductor die. As shown in
At step 640, an integrated voltage regulator die is bonded over the second semiconductor die and the insulating layer. As shown in
In the embodiments disclosed herein, the through vias 120 are arranged outside the top semiconductor die that includes the top semiconductor device. As such, the processing steps, the size, and the cost of packaging may be reduced and also the form factor may be improved.
As such, the packaged semiconductor may be used in advanced networking and server applications (e.g., AI (Artificial Intelligence)) which operate with high data rates, high bandwidth demands and low latency. Furthermore, the packaged semiconductor device may be provided with a high degree of chip package integration in a small form factor.
According to an embodiment, a semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. The semiconductor package also includes an integrated voltage regulator die bonded over the second semiconductor die and a first through via on the first semiconductor die and electrically coupled to the first semiconductor die. The first through via is disposed outside of and adjacent to the second semiconductor die and the first through via electrically couples the first semiconductor die to the first power rail structure of the second semiconductor die through the integrated voltage regulator die.
In an embodiment, the semiconductor package further includes a second through via on the first semiconductor die and a third semiconductor die that includes a second backside interconnect structure having a second power rail structure that is bonded over the first semiconductor die. The first through via and the second through via are disposed between the second semiconductor die and the third semiconductor die and the second through via electrically couples the first semiconductor die to second power rail structure of the third semiconductor die through the integrated voltage regulator die. In an embodiment, the semiconductor package further includes an insulating layer on the first semiconductor die between the second semiconductor die and the third semiconductor die such that the first through via and the second through via extend through the insulating layer. In an embodiment, the first semiconductor die further includes one or more connector bumps connected to a bottom side of the first semiconductor die and one or more third through vias that are extended between a connector bump and at bottom of the first semiconductor die to a first front-side interconnect structure of the first semiconductor die. In an embodiment, the semiconductor package further includes a fourth semiconductor die that includes a second front-side interconnect structure and one or more second vias such that the fourth semiconductor die is bonded over the first semiconductor die. The second front-side interconnect structure is away from the first semiconductor die, the first through via is arranged between the second and fourth semiconductor dies, and the one or more second vias electrically connect the first front-side interconnect structure of the first semiconductor die to the second front-side interconnect structure of the fourth semiconductor die. In an embodiment, the integrated voltage regulator die is bonded over the second semiconductor die by dielectric-to-dielectric and metal-to-metal bonding. In an embodiment, the integrated voltage regulator die provides electrical power to the second semiconductor die.
According to an embodiment, a semiconductor package includes a first semiconductor die that includes a first front-side interconnect structure. The semiconductor package includes a second semiconductor die and a third semiconductor die, separated by a distance, that are bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure and the third semiconductor die includes a second backside interconnect structure having a second power rail structure. The semiconductor package also includes an integrated voltage regulator die bonded over the second semiconductor die and the third semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure and the second power rail structure. The semiconductor package further includes one or more through vias arranged on the first front-side interconnect structure of the first semiconductor die and the one or more through vias electrically couple the first power rail structure and the second power rail structure to the first front-side interconnect structure of the first semiconductor die.
In an embodiment, the semiconductor package further includes an insulating layer on the first semiconductor die in the distance between the second semiconductor die and the third semiconductor die such that the one or more through vias extend through the insulating layer. In an embodiment, the semiconductor package further includes a first insulating bonding layer over the second semiconductor die and the third semiconductor die and first bond pads in the first insulating bonding layer such that the one or more through vias extend from the first bond pads to the first semiconductor die. In an embodiment, the integrated voltage regulator includes a second front-side interconnect structure and a second insulating bonding layer connected to the second front-side interconnect structure. The second insulating bonding layer includes second bond pads, the second insulating bonding layer is directly bonded to the first insulating bonding layer, and the second bond pads are directly bonded to the first bond pads. In an embodiment, the one or more through vias are arranged in the distance between the second semiconductor die and the third semiconductor die. In an embodiment, the one or more through vias are arranged on an opposite side of the second semiconductor die with respect to the third semiconductor die. In an embodiment, the semiconductor package further includes a plurality of connector bumps connected to a side of the first semiconductor die opposite to the first front-side interconnect structure and a plurality of second through vias extending between the first front-side interconnect structure and the plurality of connector bumps.
According to an embodiment, a method of packaging includes bonding a first semiconductor die to a second semiconductor die such that the first semiconductor die includes a first front-side interconnect structure and the second semiconductor die includes a first backside interconnect structure having a first power rail structure. The method also includes depositing an insulating layer over the first semiconductor die and next to the second semiconductor die and forming a first through via in the insulating layer such that a first end of the first through via is electrically coupled to the first front-side interconnect structure of first semiconductor die. The method further includes bonding an integrated voltage regulator die over the second semiconductor die and the insulating layer such that a second end, opposite to the first end, of the first through via is electrically connected, through the integrated voltage regulator die, to the first power rail structure in the first backside interconnect structure of the second semiconductor die.
In an embodiment, bonding the first semiconductor die to the second semiconductor die includes dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the dielectric-to-dielectric bonding includes bonding a first insulating bonding layer between a second front-side interconnect structure of the second semiconductor die and a second insulating bonding layer on the first front-side interconnect structure of the first semiconductor die, and the metal-to-metal bonding includes electrically connecting first bond pads in the first insulating bonding layer to second bond pads in the second insulating bonding layer. In an embodiment, the method of packaging further includes bonding a second front-side interconnect structure of a third semiconductor die to the first front-side interconnect structure of the first semiconductor die such that the third semiconductor die incudes a second backside interconnect structure having a second power rail structure, bonding the integrated voltage regulator die over the third semiconductor die, and forming a second through via in the insulating layer. A first end of the second through via is electrically coupled to the first front-side interconnect structure of the first semiconductor die, and a second end, opposite to the first end, of the second through via is electrically connected, through the integrated voltage regulator die, to the second power rail structure in the second backside interconnect structure of the third semiconductor die. In an embodiment, the method of packaging further includes bonding a backside of a third semiconductor die to the first front-side interconnect structure of the first semiconductor die. The third semiconductor die includes second through vias that electrically connect the first front-side interconnect structure of the first semiconductor die to a second front-side interconnect structure of the third semiconductor die. In an embodiment, the method of packaging further includes forming a plurality of third through vias in the first semiconductor die and coupling a plurality of connector bumps to a side of the first semiconductor die opposite to the first front-side interconnect structure such that the third through vias electrically connect the first front-side interconnect structure to the plurality of connector bumps.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/582,010, filed on Sep. 12, 2023, entitled “SPR (Super Power Rail) with IVR (Integrated Voltage Regulator) in SolC,” which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63582010 | Sep 2023 | US |
