Patent Application
20050151268
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to a wafer-level assembly method for chip-size, leadless devices having chips flip-assembled without bumps.
The fabrication of semiconductor devices is commonly based on assembly and packaging of individual semiconductor chips. One type of such assembly is the flip-chip technology, which uses either solder bumps (often referred to as solder balls) or gold bumps to attach the chip to a substrate, or to attach a package device to an external part.
There are several issues with the bumped flip-chip approach. First, the technology is expensive compared to conventional wire bonding assembly. The typical solder bumping process is very equipment intensive, resulting in a large capital cost. The application of pre-fabricated solder balls and the evaporation, plating, or screening of solder material are environmentally unfriendly in that they make use of excess of solder, often containing lead. Both processing and clean-up costs are high in these operations.
Second, the manufacturing of flip-chip assembly can have a long cycle time. Typically, reflows which are carried out in infrared or forced convection ovens have cycle times of 5 minutes or longer. These furnaces are usually very long (>3 m) and massive structures, occupying much space on the assembly floor. Moving parts in such furnaces are a significant source of particulate contamination.
Third, several metallurgical solder fillets contain brittle compounds and are thus at risk of bond failures. An example is tin-containing solder reacting with gold bumps. Generally, interconnections based on bumps are prone to fatigue and to develop microcracks, when exposed to thermo-mechanical stress in temperature cycle tests and device operation. As a remedy following the solder reflow step, flipped chips often use a polymeric underfill between the chip and the interposer or board to alleviate mechanical stress caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the interposer, if any, and the board. Some reliability problems occur due to the stress caused by the underfill process itself.
Another problem is caused by the ongoing trend to shrink the size of current packaging architectures. This shrinkage affects the board area consumed by the package, as well as the height needed by assembled devices. Obviously, tall interconnection bumps, which are favored for stress tolerance, are inimical to shrinking the height contour of assembled parts; further, removing the heat during device operation is aggravated by small package sizes and/or the lack of good heat conductors.
A need thus exists for an assembly and packaging strategy to create a low-cost flip-chip technology, preferably without solder or gold bumps, resulting in devices of small area and height contours combined with good thermal dissipation capabilities. Preferably this strategy should be flexible enough to be applied to wafer-scale assembly, potentially in the clean room facilities of the wafer fab itself, and true chip-size packages.
One embodiment of the invention is a method for assembling a whole wafer with a plurality of device units having metal contact pads. Each contact pad has a patterned barrier metal layer and a metal stud (preferably copper or nickel) with an outer surface suitable to form metallurgical bonds without melting are on each pad. A leadframe suitable for the whole wafer is provided, which has a plurality of segments groups, each group suitable for one device unit; each segment has first and second ends covered by solderable metal. A predetermined amount of solder paste is placed on each of the first segment ends. The leadframe is then aligned with the wafer so that each of the paste-covered segment ends is aligned with the corresponding metal stud of the respective device unit. The leadframe is connected to the wafer and the whole wafer is encapsulated so that the device units and the first segment ends are covered, while the second segment ends remain exposed. The encapsulated wafer is separated into individual device units, resulting in a plurality of chip-size devices.
The method includes the assembly of extra-thin silicon wafers, a welcome contribution for fabricating low-height chip-size devices. Further, the method may comprise the attachment of a heat spreading metal sheet to the wafer surface opposite the active surface. This step is performed prior to the step of encapsulation.
Another embodiment of the invention is a method for assembling a semiconductor device by providing a chip, which has an active surface protected by an overcoat with a plurality of windows to expose the metal contact pads. On each pad are a patterned barrier layer and a metal stud with an outer surface suitable to form metallurgical bonds without melting. In addition, a leadframe with a plurality of segments is provided, each segment having first and second ends covered by solderable metal. A predetermined amount of solder paste is placed on each of the first segment ends; the leadframe is then aligned with the chip so that each of the paste-covered segment ends is aligned with the corresponding chip metal stud. The chip is then connected to the leadframe by contacting the metal studs and the first segment ends and reflowing the solder paste. Finally, chip and first segment ends are encapsulated by a molding compound, while leaving the second segment ends are left exposed.
Another embodiment of the invention is a semiconductor device comprising a semiconductor chip having an active surface protected by an overcoat, which has a plurality of windows exposing the metal contact pads. A patterned barrier layer is on the pad metal in the windows and on those portions of the overcoat, which surround the perimeter of the windows. The chip has a plurality of patterned metal studs, one stud each on a barrier layer and each stud having an outer surface suitable to form metallurgical bonds without melting. The device has further a plurality of leadframe segments, which have first and second ends. The first end of each segment is connected to one of the studs on the contact pads, respectively. Chip and leadframe segments are encapsulated by a molding compound except for the second end of each segment, which remains exposed.
The metal contact pads may comprise either aluminum, or copper, or an alloy thereof; the stud metal may comprise either copper or nickel. The segment-to-stud connection is provided by reflowable metal, which preferably comprises a mixture of flux and one or more of the metals tin, indium, bismuth, silver, and lead. The paste smoothes any uneven surface contour of the patterned stud.
It is a technical advantage of the present invention that a wide variety of materials and techniques can be employed for the proposed metallization and assembly steps.
Other technical advantages of the present invention include a reduction of manufacturing cost, a lead-free assembly solution, improved thermal performance of the package, and improved reliability of the device.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
The present invention is related to U.S. patent Applications No. 10/001,302, filed on Oct. 01, 2001 (Zuniga-Ortiz et al., “Bumpless Wafer Scale Device and Board Assembly”); No. 10/057,138, filed on Jan. 25, 2002 (Zuniga-Ortiz et al., “Flip-Chip without Bumps and Polymer for Board Assembly”); No. 10/678,709, filed on Oct. 3, 2003 (Bojkov et al., “Sealing and Protecting Integrated Circuit Bonding Pads”); and No. 10/689,386, filed on Oct. 20, 2003 (Bojkov et al., “Direct Bumping on Integrated Circuit Contacts Enabled by Metal-to-Insulator Adhesion”).
The schematic cross section of
The encapsulated wafer is separated into individual device units, thereby creating a plurality of assembled, packaged semiconductor devices. The preferred method for wafer separation is a sawing technique, which is indicated in
The schematic cross section of
The encapsulated wafer is separated into individual device units, thereby creating a plurality of assembled, packaged semiconductor devices. The preferred method for wafer separation is a sawing technique, which is indicated in
Another embodiment of the invention is a method for assembling semiconductor devices as depicted in the process flow block diagram of
In step 303 of this method, a leadframe is provided, which is suitable for the whole wafer. This leadframe has a plurality of segment groups, each group suitable for one of the device units; each segment has first and second ends covered by solderable metal. Preferred metal for the leadframe and the segments is nickel-plated copper.
In step 304 of the method, a predetermined amount of solder paste is placed on each of the first segment ends. Preferred pastes comprise flux and one or more of the metals tin, indium, bismuth, and silver (and lead, if necessary). The leadframe is then aligned in step 305 with the wafer so that each of the paste-covered segment ends is aligned with the corresponding metal stud of the respective device unit. The leadframe is connected in step 306 to the wafer by contacting the metal studs and the first segment ends and then reflowing the solder paste.
Next, in process step 307, the whole wafer is encapsulated, preferably in a molding compound, so that the device units and the first segment ends are covered, while the second segment ends remain exposed. Finally in step 308 of
In an additional process step prior to step 307 of encapsulating, a metal sheet intended as a heat spreader is be attached to the wafer so that one sheet surface is adhered to the passive chip surface opposite the active surface, while the sheet surface opposite the adhered surface remains exposed. During the singulation step, the saw (or laser, etc.) cuts through the sheet, the wafer and the leadframe in the same process step. In the finished device, the spreader can act as heat radiator or is available for connection to an external heat sink.
Another embodiment of the invention is a method for assembling a semiconductor device as depicted in the process flow block diagram of
In step 403 of this method, a leadframe is provided, which has a plurality of segments; each segment has first and second ends covered by solderable metal. Preferred metal for the segments is nickel-plated copper.
In step 404 of the method, a predetermined amount of solder paste is placed on each of the first segment ends. Preferred pastes comprise flux and one or more of the metals tin, indium, bismuth, and silver (and lead, if necessary). The leadframe is then aligned in step 405 with the chip so that each of said paste-covered segment ends is aligned with the corresponding chip metal stud. The leadframe is connected in step 406 to the chip by contacting the metal studs and the first segment ends and then reflowing the solder paste.
Finally, in step 407, the chip and the first segment ends are encapsulated, preferably by a molding compound, while leaving the second segment ends exposed. The method of
In an additional process step prior to step 407 of encapsulating, a heat spreader may be attached to the chip so that one heat spreader surface is adhered to the passive chip surface opposite the active surface, while the spreader surface opposite the adhered surface remains exposed. The spreader can thus act as heat radiator, or is available for connection to an external heat sink.
Another embodiment of the invention uses more than one chip in the process flow of
The bump-less assembly of the present invention can be most easily appreciated by highlighting the shortcomings of the known technology. As a typical example of the known technology, the schematic cross section of
A patterned “under-bump” metallization 503 over the aluminum or copper metallization 504 of the circuit contact pads consists of a sequence of several layers: When the circuit metallization 504 is aluminum, the conformal layer 505 adjacent to the circuit is typically a refractory metal 505, such as chromium, titanium, tungsten, molybdenum, tantalum, or alloys thereof. When the circuit metallization 504 is copper, the conformal layer 505 is typically aluminum, or copper on a carefully cleaned copper metallization. The following buffer layer 506 is typically nickel. The outermost layer 507 has to be a solderable metal, such as gold, copper, nickel, or palladium.
Finally, solder bump 509 is formed by reflowing the deposited (evaporated or plated) or attached solder alloy (typically a mixture of tin and lead, indium, or other metals). These solder bumps assume various shapes after attaching the chip to the substrate, influenced by the forces of surface tension during the reflow process.
The overall process to fabricate the contact pad depicted in
In some process flows of the known technology, a layer 508 of polymeric material (benzocyclobutene, BCB) is deposited over the silicon nitride layer 502 so that it can act as a stress-relieving buffer between the under-bump metal 503 and the solder material 509. It has been shown to be useful in reducing solder joint failures when the solder bump has to withstand thermomechanical stresses in temperature variations.
The bumped chip is then flipped so that the active chip surface, including the integrated circuit, faces the substrate or assembly board 510, consisting in its bulk of insulating material. Substrate 510 has a metal contact pad 511, typically copper, which has a solderable surface 512, commonly a gold layer. Usually, some amount of solder paste is deposited on layer 512. Solder ball 509 is brought in contact with layer 512 and reflowed. After cool-down, the solder connection may have the contours depicted in the example of
The schematic cross section of
The process step of attaching gold bump 520 to the surface layer 512 of the substrate contact pad is usually performed with the aid of tin-containing solder paste in order to keep attachment time short and temperature low. The resulting fillet of the contact joint comprise gold/tin alloys which are mechanically brittle and thus put the reliability of the joint at risk.
The schematic cross section of
Overcoat 602 has a plurality of windows 602a, which expose the metallization 604. One or more conductive barrier layers 605 and 606 are on the metallization 604 exposed by the windows; these barrier layers are patterned so that they also cover the walls of the windows and a distance 602b of the insulator 602 surrounding the perimeter of the window. Preferred metals of the barrier layer are titanium/tungsten alloys; other choices include titanium, tungsten, tantalum, molybdenum, chromium, vanadium, alloys thereof, stacked layers thereof, and chemical compounds of these metals. The thickness of these one or more layers of metals is in the range from about 10 to 30 nm.
Attached to the outermost barrier layer of each window is a patterned metal stud 620. The preferred metal for stud 620 is copper or a copper alloy; alternatively, stud 620 is made of nickel or a nickel alloy. The preferred thickness range for stud 620 is between about 20 and 50 μm. Stud 620 has an outer surface 620a, which provides the ability to form metallurgical bonds without melting. This ability preferably is conveyed by a deposited metal film 621, which is preferably selected from a group consisting of a layer of nickel followed by an outermost layer of gold, and a layer of nickel followed by a layer of palladium and an outermost layer of gold. Other choices include silver or platinum. The thickness of film 621 is preferably less than 15 nm.
Further shown in
Base metal has preferred thickness range from 100 to 300 μm; thinner sheets are possible. The plated layer is made of a bondable and solderable electronegative metal, covering the base metal and typically having a thickness between 0.2 and 1.0 μm. Preferred metals include nickel, cobalt and alloys thereof. Nickel in particular is favored because it reduces, when placed under tin or a tin-rich solder, the propensity for tin whiskers.
The leadframe segments are typically stamped or etched from a starting sheet of metal. Each segment has first and second ends; the first end serves the connection to the chip and the second end serves the connection to externals parts.
The metallurgical connection between chip contact stud 620 (with layer 621) and leadframe segment 610 is provided by reflowable metal 630, which is preferably a solder paste comprising a mixture of flux and one or more metals tin, indium, bismuth, and silver. During the reflow process, paste metals 630 may form meniscus 630a, and also smoothen any uneven surface contour, such as the step-like contour of the patterned stud 620 shown in
The schematic and simplified
As a result, device 700 is a leadless component flip-assembled without bumps (solder or gold). Due to the lack of bumps and protruding leads, the thickness 710 of device 700 can be made small. The preferred device thickness range is from 0.5 to 1.0 mm. Device thickness 710 can be reduced below 0.5 mm, when the chip thickness 711 is less than about 0.25 mm and the molding compound thickness 712 is less than about 0.20 mm.
As another embodiment of the invention, the schematic and simplified
As a result, device 800 is a leadless component, flip-assembled without bumps and distinguished by excellent thermal characteristics. Due to the lack of bumps and protruding leads, the thickness 810 of device 800 can be made small. The preferred device thickness range is from 0.5 to 1.0 mm. Device thickness 810 can be reduced below 0.5 mm, when chips with thickness 811 less than about 0.25 mm and heat spreaders with thickness 822 less than about 0.20 mm are used.
While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications and embodiments.
| Number | Date | Country | |
|---|---|---|---|
| 60535572 | Jan 2004 | US |
