WIRING SUBSTRATE HAVING VARIOUSLY SIZED BALL PADS, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND STACK PACKAGE USING THE SEMICONDUCTOR PACKAGE

Abstract

A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a bottom view showing a wiring substrate for a semiconductor package according to an example embodiment of the present invention.

FIG. 2 is an enlarged view of the portion ‘A’ of FIG. 1.

FIG. 3 is a sectional view of the wiring substrate of FIG. 1 taken along the line III-III

FIG. 4 is a top view showing a semiconductor package having the wiring substrate of FIG. 1.

FIG. 5 is a sectional view of the semiconductor package of FIG. 4 taken along the line V-V.

FIG. 6 is a sectional view showing a state in which the semiconductor package of FIG. 4 is mounted on a motherboard.

FIG. 7 is a sectional view showing a stack package using the semiconductor package of FIG. 4 as a lower package.

FIG. 8 is a sectional view showing a state in which the stack package of FIG.7 is mounted on a motherboard.

Claims

1. A wiring substrate having variously sized ball pads comprising: a substrate body having an upper surface and lower surface;a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip; andconductive wiring layers having bonding pads formed inside the resin encapsulating area and electrically connectable to a semiconductor chip when disposed within the resin encapsulating area, upper ball pads formed on the upper surface and outside the resin encapsulating area, and lower ball pads formed on the lower surface of the substrate body,wherein the lower ball pads include inner ball pads formed on a first area corresponding to the resin encapsulating area, and outer ball pads formed on a second area corresponding to an area outside the resin encapsulating area and formed to have relatively greater surface areas than the inner ball pads, the outer ball pads including first outer ball pads formed on areas along each side of the lower surface and second outer ball pads formed at the corners of the lower surface to form substantially square shapes in combination with the first outer ball pads, the second outer ball pads being formed to have a greater surface area than the first outer ball pads.

2. The wiring substrate of claim 1, wherein the second outer ball pads are formed to have the greatest surface area among the lower ball pads.

3. The wiring substrate of claim 2, wherein the outer ball pads are formed in a plurality of rows.

4. The wiring substrate of claim 2, wherein the inner ball pads comprise first inner ball pads formed at a predetermined distance from the outer ball pads, the first inner ball pads comprising side first inner ball pads formed on areas corresponding to the first outer ball pads, and corner first inner ball pads formed on areas corresponding to the second outer ball pads to form square shapes in combination with the side first inner ball pads and formed to a have greater surface area than the side first inner ball pads.

5. The wiring substrate of claim 4, wherein the first inner ball pads are formed in a plurality of rows.

6. The wiring substrate of claim 4, wherein the inner ball pads further include second inner ball pads formed on the central part of the first inner ball pads, the second inner ball pads having a smaller surface area than the first inner ball pads.

7. The wiring substrate of claim 4, wherein the area containing the second outer ball pads is greater than the area containing the corner first inner ball pads.

8. The wiring substrate of claim 1, wherein the wiring substrate further comprises insulating protection layers covering both surfaces of the substrate body including the conductive wiring layers except the bonding pads, upper ball pads and lower ball pads.

9. The wiring substrate of claim 1, wherein the second outer ball pads include dummy ball pads formed proximate to the outermost corners of the lower surface.

10. The wiring substrate of claim 1, wherein the upper ball pads include dummy ball pads formed proximate to the outermost corners of the upper surface.

11. A semiconductor package comprising: a wiring substrate having variously sized ball pads comprising: a substrate body having an upper surface and lower surface;a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip; andconductive wiring layers having bonding pads formed inside the resin encapsulating area and electrically connectable to a semiconductor chip when disposed within the resin encapsulating area, upper ball pads formed on the upper surface and outside the resin encapsulating area, and lower ball pads formed on the lower surface of the substrate body,wherein the lower ball pads include inner ball pads formed on a first area corresponding to the resin encapsulating area, and outer ball pads formed on a second area corresponding to an area outside the resin encapsulating area and formed to have relatively greater surface areas than the inner ball pads, the outer ball pads including first outer ball pads formed on areas along each side of the lower surface and second outer ball pads formed proximate to the corners of the lower surface to form square-like shapes in combination with the first outer ball pads, the second outer ball pads being formed to have a greater surface area than the first outer ball pads, the wiring substrate including insulating protection layers covering the upper and lower surfaces of the substrate body including the conductive wiring layers except the bonding pads, upper ball pads and lower ball pads;a semiconductor chip mounted on the resin encapsulating area of the wiring substrate;a resin encapsulating section sealing the resin encapsulating area including the semiconductor chip; andsolder balls formed on lower ball pads or the wiring substrate.

12. The semiconductor package of claim 11, wherein the second outer ball pads include dummy ball pads formed proximate to the outermost corners of the lower surface of the wiring substrate.

13. The semiconductor package of claim 12, wherein the solder balls include dummy solder balls connected to the dummy ball pads.

14. The semiconductor package of claim 11, wherein the upper ball pads include dummy ball pads formed proximate to the outermost corners of the upper surface of the wiring substrate.

15. The semiconductor package of claim 11 further comprising: an upper package stacked on the upper ball pads of the package of claim 11 and coupled thereto by solder bonding.

16. The stack package of claim 15, wherein the upper package is a ball grid array type semiconductor package having solder balls on the lower surface corresponding to the upper ball pads.

17. The stack package of claim 16, wherein the second outer ball pads include dummy ball pads formed proximate to the outermost corners of the lower surface of the wiring substrate.

18. The stack package of claim 17, wherein the solder balls of the lower package include dummy solder balls connected to the dummy ball pads.

19. The stack package of claim 15, wherein the upper ball pads of the lower package include dummy ball pads formed proximate to the outermost corners of the upper surface of the wiring substrate.

20. The stack package of claim 19, wherein solder balls of the upper package include dummy solder balls connected to the dummy ball pads.

21. A wiring substrate having variously sized ball pads comprising: a substrate body having an upper surface and lower surface;a resin encapsulating area disposed on the central part of the upper surface of the substrate body; andconductive wiring layers including upper ball pads formed outside the resin encapsulating area, and lower ball pads formed on the lower surface of the substrate body,wherein the lower ball pads formed proximate to the corners of the lower surface are formed to have relatively greater surface areas than those formed at other areas.

22. The wiring substrate of claim 21, wherein the lower ball pads comprise: inner ball pads formed on the area corresponding to the resin encapsulating area; andouter ball pads formed on the area corresponding to an area outside the resin encapsulating area to form square shapes, and formed to have relatively greater surface areas than the inner ball pads, the outer ball pads formed proximate to the corners of the lower surface being formed to have a relatively greater surface area than those at other areas.

23. The wiring substrate of claim 22, wherein the outer ball pads formed proximate to the corners of the lower surface are formed to have the greatest surface area.

24. A semiconductor package comprising: a wiring substrate having variously sized ball pads and comprising: a substrate body having an upper surface and lower surface;a resin encapsulating area disposed on the central part of the upper surface of the substrate body; andconductive wiring layers including upper ball pads formed outside the resin encapsulating area, and lower ball pads formed on the lower surface of the substrate body,wherein the lower ball pads formed proximate to the corners of the lower surface are formed to have relatively greater surface areas than those formed at other areas;a semiconductor chip mounted on the resin encapsulating area of the wiring substrate;a resin encapsulating section sealing the resin encapsulating area including the semiconductor chip; andsolder balls formed on lower ball pads of the wiring substrate.

25. The semiconductor package of claim 24, wherein the lower ball pads comprise: inner ball pads formed on the area corresponding to the resin encapsulating area; andouter ball pads formed on the area corresponding to an area outside the resin encapsulating area to form square shapes and formed to have relatively greater surface areas than the inner ball pads, the outer ball pads formed proximate to the corners of the lower surface being formed to have a relatively greater surface area than those formed at other areas.

26. The semiconductor package of claim 25, wherein the outer ball pads at the corners of the lower surface of the wiring substrate are formed to have the greatest surface area among the lower ball pads.

27. The semiconductor package of claim 24 further comprising: an upper package stacked on upper ball pads of the package of claim 24 and coupled thereto by solder bonding.

28. The stack package of claim 27, wherein the upper package is a ball grid array type semiconductor package formed with solder balls on the lower surface corresponding to the upper ball pads.

29. The stack package of claim 27, wherein lower ball pads of the lower package comprise: inner ball pads formed on the area corresponding to the resin encapsulating area; andouter ball pads formed on the area corresponding to an area outside the resin encapsulating area to form square shapes, and formed to have relatively greater surface areas than the inner ball pads, the outer ball pads formed proximate to the corners of the lower surface being formed to have a relatively greater surface area than those formed at other areas.

30. The stack package of claim 29, wherein the outer ball pads formed proximate to the corners of the lower surface of the wring substrate are formed to have the greatest surface area.

31. In a semiconductor package having opposing pads to be interconnected by way of solder balls therebetween with pad surface area selected according to a given function of separation between opposing pads, a method of pad formation comprising: selecting a corner set of pads and an edge set of pads, separation between opposing members of said edge set being similar to separation between opposing members of said corner set and producing according to said given function given pad surface areas, said edge set of pads having said given surface area, said corner set of pads having a surface area greater than said given surface area.

32. A method of pad formation according to claim 31 wherein said corner set of pads includes dummy pads.