Pushkar Ranade

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 10,325,986
- Issue date Jun 18, 2019
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,217,838
- Issue date Feb 26, 2019
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,014,387
- Issue date Jul 3, 2018
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,991,300
- Issue date Jun 5, 2018
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transistor with threshold voltage set notch and method of fabricati...
- Patent number 9,922,977
- Issue date Mar 20, 2018
- Mie Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power semiconductor transistor structure and method of fabricat...
- Patent number 9,865,596
- Issue date Jan 9, 2018
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,812,550
- Issue date Nov 7, 2017
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing or eliminating pre-amorphization in transistor manufacture
- Patent number 9,793,172
- Issue date Oct 17, 2017
- Mie Fujitsu Semiconductor Limited
- Lance Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,786,703
- Issue date Oct 10, 2017
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing or eliminating pre-amorphization in transistor manufacture
- Patent number 9,514,940
- Issue date Dec 6, 2016
- Mie Fujitsu Semiconductor Limited
- Lance S. Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 9,508,800
- Issue date Nov 29, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,508,728
- Issue date Nov 29, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power semiconductor transistor structure and method of fabricat...
- Patent number 9,496,261
- Issue date Nov 15, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,478,571
- Issue date Oct 25, 2016
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with threshold voltage set notch and method of fabricati...
- Patent number 9,418,987
- Issue date Aug 16, 2016
- Mie Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating multiple transistor devices on a substrate w...
- Patent number 9,406,567
- Issue date Aug 2, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 9,391,076
- Issue date Jul 12, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits having a plurality of high-K metal gate FETs wi...
- Patent number 9,385,047
- Issue date Jul 5, 2016
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor with reduced junction leakage c...
- Patent number 9,368,624
- Issue date Jun 14, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,299,698
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,281,248
- Issue date Mar 8, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 9,263,523
- Issue date Feb 16, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method of fabrication thereof with mixe...
- Patent number 9,224,733
- Issue date Dec 29, 2015
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High uniformity screen and epitaxial layers for CMOS devices
- Patent number 9,196,727
- Issue date Nov 24, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with improved channel stack and method for...
- Patent number 9,111,785
- Issue date Aug 18, 2015
- Mie Fujitsu Semiconductor Limited
- Paul E. Gregory
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with dopant migration suppression and method...
- Patent number 9,112,057
- Issue date Aug 18, 2015
- Mie Fujitsu Semiconductor Limited
- Sameer Pradhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with reduced junction leakage and method of...
- Patent number 9,105,711
- Issue date Aug 11, 2015
- Mie Fujitsu Semiconductor Limited
- Lingquan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits having a plurality of high-K metal gate FETs wi...
- Patent number 9,093,550
- Issue date Jul 28, 2015
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deeply depleted MOS transistors having a screening layer and method...
- Patent number 9,041,126
- Issue date May 26, 2015
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source/drain extension control for advanced transistors
- Patent number 9,006,843
- Issue date Apr 14, 2015
- SuVolta, Inc.
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Structure With Multiple Transistors Having Various Th...
- Publication number 20180261683
- Publication date Sep 13, 2018
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Channel Deeply Depleted Channel Transistor
- Publication number 20170323916
- Publication date Nov 9, 2017
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20170141209
- Publication date May 18, 2017
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing or Eliminating Pre-Amorphization in Transistor Manufacture
- Publication number 20170040225
- Publication date Feb 9, 2017
- MIE Fujitsu Semiconductor Limited
- Lance Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Advanced Transistors with Punch Through Suppression
- Publication number 20170040419
- Publication date Feb 9, 2017
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Channel Deeply Depleted Channel Transistor
- Publication number 20170025457
- Publication date Jan 26, 2017
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Power Semiconductor Transistor Structure and Method of Fabricat...
- Publication number 20170012044
- Publication date Jan 12, 2017
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor with Threshold Voltage Set Notch and Method of Fabricati...
- Publication number 20160336318
- Publication date Nov 17, 2016
- MIE Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Structures and Processes Based on Selective Thinning
- Publication number 20160307907
- Publication date Oct 20, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE
- Publication number 20160268133
- Publication date Sep 15, 2016
- MIE Fujitsu Semiconductor Limited
- Lance S. Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Epitaxial Channel Transistors and Die With Diffusion Doped Channels
- Publication number 20160211346
- Publication date Jul 21, 2016
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Advanced Transistors with Punch Through Suppression
- Publication number 20160181370
- Publication date Jun 23, 2016
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20160163823
- Publication date Jun 9, 2016
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Gate Stack Structures and Processes
- Publication number 20160141292
- Publication date May 19, 2016
- MIE Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES
- Publication number 20150340460
- Publication date Nov 26, 2015
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Uniformity Screen and Epitaxial Layers for CMOS Devices
- Publication number 20150333144
- Publication date Nov 19, 2015
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuits Having a Plurality of High-K Metal Gate FETs wi...
- Publication number 20150287645
- Publication date Oct 8, 2015
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES
- Publication number 20150061012
- Publication date Mar 5, 2015
- SUVOLTA, INC.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATI...
- Publication number 20140284722
- Publication date Sep 25, 2014
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS
- Publication number 20140167157
- Publication date Jun 19, 2014
- SUVOLTA, INC.
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
- Publication number 20140167156
- Publication date Jun 19, 2014
- SuVolta, lnc.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF...
- Publication number 20140103406
- Publication date Apr 17, 2014
- Lingquan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...
- Publication number 20140084385
- Publication date Mar 27, 2014
- SUVOLTA, INC.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE
- Publication number 20140038386
- Publication date Feb 6, 2014
- SUVOLTA, INC.
- Lance S. Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXE...
- Publication number 20140035060
- Publication date Feb 6, 2014
- SUVOLTA, INC.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS
- Publication number 20140015067
- Publication date Jan 16, 2014
- SUVOLTA, INC.
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...
- Publication number 20140001571
- Publication date Jan 2, 2014
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICAT...
- Publication number 20130328129
- Publication date Dec 12, 2013
- SUVOLTA, INC.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR...
- Publication number 20130313652
- Publication date Nov 28, 2013
- Paul E. Gregory
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
- Publication number 20130181298
- Publication date Jul 18, 2013
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS

Pushkar Ranade

Person

Patents Grantslast 30 patents

Advanced transistors with punch through suppression

Semiconductor structure with multiple transistors having various th...

Semiconductor structure with multiple transistors having various th...

Buried channel deeply depleted channel transistor

Transistor with threshold voltage set notch and method of fabricati...

Low power semiconductor transistor structure and method of fabricat...

Semiconductor structure with multiple transistors having various th...

Reducing or eliminating pre-amorphization in transistor manufacture

Buried channel deeply depleted channel transistor

Reducing or eliminating pre-amorphization in transistor manufacture

Advanced transistors with punch through suppression

CMOS gate stack structures and processes

Low power semiconductor transistor structure and method of fabricat...

Buried channel deeply depleted channel transistor

Transistor with threshold voltage set notch and method of fabricati...

Method for fabricating multiple transistor devices on a substrate w...

CMOS structures and processes based on selective thinning

Integrated circuits having a plurality of high-K metal gate FETs wi...

Method for fabricating a transistor with reduced junction leakage c...

Semiconductor structure with multiple transistors having various th...

CMOS gate stack structures and processes

Advanced transistors with punch through suppression

Semiconductor structure and method of fabrication thereof with mixe...

High uniformity screen and epitaxial layers for CMOS devices

Semiconductor structure with improved channel stack and method for...

Semiconductor devices with dopant migration suppression and method...

Semiconductor structure with reduced junction leakage and method of...

Integrated circuits having a plurality of high-K metal gate FETs wi...

Deeply depleted MOS transistors having a screening layer and method...

Source/drain extension control for advanced transistors

Patents Applicationslast 30 patents

Semiconductor Structure With Multiple Transistors Having Various Th...

Buried Channel Deeply Depleted Channel Transistor

Semiconductor Structure with Multiple Transistors Having Various Th...

Reducing or Eliminating Pre-Amorphization in Transistor Manufacture

Advanced Transistors with Punch Through Suppression

Buried Channel Deeply Depleted Channel Transistor

Low Power Semiconductor Transistor Structure and Method of Fabricat...

Transistor with Threshold Voltage Set Notch and Method of Fabricati...

CMOS Structures and Processes Based on Selective Thinning

REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE

Epitaxial Channel Transistors and Die With Diffusion Doped Channels

Advanced Transistors with Punch Through Suppression

Semiconductor Structure with Multiple Transistors Having Various Th...

CMOS Gate Stack Structures and Processes

ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES

High Uniformity Screen and Epitaxial Layers for CMOS Devices

Integrated Circuits Having a Plurality of High-K Metal Gate FETs wi...

HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES

TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATI...

SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS

ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION

SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF...

DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...

REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE

SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXE...

SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS

SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...

LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICAT...

SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR...

ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION