Thomas Hoffmann

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selectable monolithic or external scalable die-to-die interconnecti...
- Patent number 12,087,689
- Issue date Sep 10, 2024
- Apple Inc.
- Sanjay Dabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable monolithic or external scalable die-to-die interconnecti...
- Patent number 11,862,557
- Issue date Jan 2, 2024
- Apple Inc.
- Sanjay Dabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor layout in FinFET technologies
- Patent number 11,720,734
- Issue date Aug 8, 2023
- Apple Inc.
- Farzan Farbiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage current reduction in electrical isolation gate structures
- Patent number 11,469,226
- Issue date Oct 11, 2022
- Apple Inc.
- Emre Alptekin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor layout in FinFET technologies
- Patent number 10,740,527
- Issue date Aug 11, 2020
- Apple Inc.
- Farzan Farbiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage current reduction in electrical isolation gate structures
- Patent number 10,700,065
- Issue date Jun 30, 2020
- Apple Inc.
- Emre Alptekin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,217,838
- Issue date Feb 26, 2019
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,014,387
- Issue date Jul 3, 2018
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor device with a tuned dopant profile
- Patent number 9,893,148
- Issue date Feb 13, 2018
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,812,550
- Issue date Nov 7, 2017
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor device with a tuned dopant profile
- Patent number 9,577,041
- Issue date Feb 21, 2017
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,508,728
- Issue date Nov 29, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating multiple transistor devices on a substrate w...
- Patent number 9,406,567
- Issue date Aug 2, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 9,391,076
- Issue date Jul 12, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor with reduced junction leakage c...
- Patent number 9,368,624
- Issue date Jun 14, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,299,698
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor device with a tuned dopant profile
- Patent number 9,299,801
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,281,248
- Issue date Mar 8, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High uniformity screen and epitaxial layers for CMOS devices
- Patent number 9,196,727
- Issue date Nov 24, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with reduced junction leakage and method of...
- Patent number 9,105,711
- Issue date Aug 11, 2015
- Mie Fujitsu Semiconductor Limited
- Lingquan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having fin structures and fabrication methods...
- Patent number 9,054,219
- Issue date Jun 9, 2015
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deeply depleted MOS transistors having a screening layer and method...
- Patent number 9,041,126
- Issue date May 26, 2015
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple transistor types formed in a common epitaxial layer by dif...
- Patent number 8,916,937
- Issue date Dec 23, 2014
- SuVolta, Inc.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having reduced junction leakage and methods of forming t...
- Patent number 8,883,600
- Issue date Nov 11, 2014
- SuVolta, Inc.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 8,735,987
- Issue date May 27, 2014
- SuVolta, Inc.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple transistor types formed in a common epitaxial layer by dif...
- Patent number 8,653,604
- Issue date Feb 18, 2014
- SuVolta, Inc.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with reduced junction leakage and method of...
- Patent number 8,637,955
- Issue date Jan 28, 2014
- SuVolta, Inc.
- Lingquan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple transistor types formed in a common epitaxial layer by dif...
- Patent number 8,629,016
- Issue date Jan 14, 2014
- SuVolta, Inc.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 8,614,128
- Issue date Dec 24, 2013
- SuVolta, Inc.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Vertical Transistors With Backside Power Delivery
- Publication number 20240105617
- Publication date Mar 28, 2024
- Apple Inc.
- Xin Miao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selectable Monolithic or External Scalable Die-to-Die Interconnecti...
- Publication number 20240047353
- Publication date Feb 8, 2024
- Apple Inc.
- Sanjay Dabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
- Publication number 20230409797
- Publication date Dec 21, 2023
- Apple Inc.
- Farzan Farbiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selectable Monolithic or External Scalable Die-to-Die Interconnecti...
- Publication number 20230085890
- Publication date Mar 23, 2023
- Apple Inc.
- Sanjay Dabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leakage Current Reduction in Electrical Isolation Gate Structures
- Publication number 20230005908
- Publication date Jan 5, 2023
- Apple Inc.
- Emre Alptekin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
- Publication number 20200401752
- Publication date Dec 24, 2020
- Apple Inc.
- Farzan Farbiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage Current Reduction in Electrical Isolation Gate Structures
- Publication number 20200328205
- Publication date Oct 15, 2020
- Apple Inc.
- Emre Alptekin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage Current Reduction in Electrical Isolation Gate Structures
- Publication number 20200118999
- Publication date Apr 16, 2020
- Apple Inc.
- Emre Alptekin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
- Publication number 20190073440
- Publication date Mar 7, 2019
- Apple Inc.
- Farzan Farbiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor Structure With Multiple Transistors Having Various Th...
- Publication number 20180261683
- Publication date Sep 13, 2018
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20170141209
- Publication date May 18, 2017
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating a Transistor Device With a Tuned Dopant Profile
- Publication number 20170025501
- Publication date Jan 26, 2017
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Structures and Processes Based on Selective Thinning
- Publication number 20160307907
- Publication date Oct 20, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating a Transistor Device With a Tuned Dopant Profile
- Publication number 20160172444
- Publication date Jun 16, 2016
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20160163823
- Publication date Jun 9, 2016
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Gate Stack Structures and Processes
- Publication number 20160141292
- Publication date May 19, 2016
- MIE Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Uniformity Screen and Epitaxial Layers for CMOS Devices
- Publication number 20150333144
- Publication date Nov 19, 2015
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES
- Publication number 20150061012
- Publication date Mar 5, 2015
- SUVOLTA, INC.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF...
- Publication number 20140103406
- Publication date Apr 17, 2014
- Lingquan Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...
- Publication number 20140084385
- Publication date Mar 27, 2014
- SUVOLTA, INC.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...
- Publication number 20140001571
- Publication date Jan 2, 2014
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS

Thomas Hoffmann

Person

Patents Grantslast 30 patents

Selectable monolithic or external scalable die-to-die interconnecti...

Selectable monolithic or external scalable die-to-die interconnecti...

Semiconductor layout in FinFET technologies

Leakage current reduction in electrical isolation gate structures

Semiconductor layout in FinFET technologies

Leakage current reduction in electrical isolation gate structures

Semiconductor structure with multiple transistors having various th...

Semiconductor structure with multiple transistors having various th...

Method for fabricating a transistor device with a tuned dopant profile

Semiconductor structure with multiple transistors having various th...

Method for fabricating a transistor device with a tuned dopant profile

CMOS gate stack structures and processes

Method for fabricating multiple transistor devices on a substrate w...

CMOS structures and processes based on selective thinning

Method for fabricating a transistor with reduced junction leakage c...

Semiconductor structure with multiple transistors having various th...

Method for fabricating a transistor device with a tuned dopant profile

CMOS gate stack structures and processes

High uniformity screen and epitaxial layers for CMOS devices

Semiconductor structure with reduced junction leakage and method of...

Semiconductor devices having fin structures and fabrication methods...

Deeply depleted MOS transistors having a screening layer and method...

Multiple transistor types formed in a common epitaxial layer by dif...

Transistor having reduced junction leakage and methods of forming t...

CMOS gate stack structures and processes

Multiple transistor types formed in a common epitaxial layer by dif...

Semiconductor structure with reduced junction leakage and method of...

Multiple transistor types formed in a common epitaxial layer by dif...

CMOS structures and processes based on selective thinning

Patents Applicationslast 30 patents

Vertical Transistors With Backside Power Delivery

Selectable Monolithic or External Scalable Die-to-Die Interconnecti...

SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES

Selectable Monolithic or External Scalable Die-to-Die Interconnecti...

Leakage Current Reduction in Electrical Isolation Gate Structures

SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES

Leakage Current Reduction in Electrical Isolation Gate Structures

Leakage Current Reduction in Electrical Isolation Gate Structures

SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES

Semiconductor Structure With Multiple Transistors Having Various Th...

Semiconductor Structure with Multiple Transistors Having Various Th...

Method for Fabricating a Transistor Device With a Tuned Dopant Profile

CMOS Structures and Processes Based on Selective Thinning

Method for Fabricating a Transistor Device With a Tuned Dopant Profile

Semiconductor Structure with Multiple Transistors Having Various Th...

CMOS Gate Stack Structures and Processes

High Uniformity Screen and Epitaxial Layers for CMOS Devices

HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES

SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF...

DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...

SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...