1. Technical Field
This disclosure generally relates to semiconductor devices, methods of making semiconductor devices, dies, wafer level packaging, embedded wafer level packaging, ball grid arrays and embedded wafer level ball grid arrays.
2. Description of the Related Art
Semiconductor devices may be produced by forming a plurality of components in or on one or more semiconductor wafers, substrates, dies, etc. Coupling pads may be formed on surfaces of the wafers, substrates or dies to facilitate packaging the semiconductor devices and/or electrically coupling the dies, wafers, etc., to other components of an electronic device or system. For example, to facilitate coupling a die, wafer, or embedded wafer level ball grid array into a semiconductor package coupled to a circuit board of an electronic system. Contact pads on surfaces of wafers, die, etc., may be used in connection with many types of semiconductor packages, including ball-grid array packages, die packages, wafer level packages, embedded wafer level packages, and embedded wafer level ball grid array packages.
In an embodiment, a method comprises: forming a dielectric region on a substrate, the dielectric region having a plurality of channels in a first surface of the dielectric region; forming a barrier region of a first conductive material on the first surface of the dielectric region and on surfaces of the plurality of channels of the dielectric region; forming a conductive region of a second conductive material different from the first conductive material on the barrier region; removing part of the conductive region to form a plurality of conductive pads of the second conductive material in the plurality of channels; removing portions of the barrier region on the first surface of the dielectric region using a first etchant; and subsequently etching surfaces of the plurality of conductive pads of the second conductive material to remove the first etchant from surfaces of the plurality of conductive pads. In an embodiment, the method further comprises forming a plurality of components in a substructure of the substrate, wherein forming the dielectric region comprises forming a dielectric layer on the substructure and forming channels through the dielectric layer to components of the plurality of components. In an embodiment, the first conductive material comprises titanium tungsten and the second conductive material comprises copper. In an embodiment, removing part of the conductive region to form a plurality of conductive pads of the second conductive material in the plurality of channels comprises etching the conductive region. In an embodiment, the first etchant comprises hydrogen peroxide. In an embodiment, etching surfaces of the plurality of conductive pads of the second conductive material comprises removing traces of the hydrogen peroxide and hydrogen peroxide byproducts from surfaces of the plurality of conductive pads. In an embodiment, the method further comprises assembling an integrated circuit package including the substrate. In an embodiment, the plurality of conductive pads of the second conductive material comprise a plurality of conductive pads of a semiconductor package ball-grid array. In an embodiment, subsequently etching surfaces of the plurality of conductive pads of the second conductive material comprises using at least one etchant selected from the group including: cupric chloride; ferric chloride; ammonium sulfate; ammonia; nitric acid; and hydrochloric acid. In an embodiment, the method further comprises: subsequently forming a plurality of conductive regions of a third conductive material on at least some of the plurality of conductive pads of the second conductive material, wherein the third conductive material is different from the second conductive material. In an embodiment, the plurality of conductive regions of a third conductive material comprise a plurality of solder balls. In an embodiment, the third conductive material comprises at least one of nickel and gold.
In an embodiment, a method comprises: forming a barrier region of a first conductive material on a substrate; forming a first plurality of conductive regions of a second conductive material, each region of the first plurality of conductive regions of the second conductive material having a first surface on the barrier region and a second surface opposite of the first surface; etching portions of the barrier region between the first plurality of conductive regions of the second conductive material using a first etchant; and subsequently etching at least the second surfaces of the first plurality of conductive regions of the second conductive material to remove the first etchant from at least the second surfaces of the first plurality of conductive regions. In an embodiment, the barrier region comprises forming a barrier layer having a plurality of channels and forming the first plurality of conductive regions of the second conductive material comprises forming conductive regions of the second conductive material in the plurality of channels of the barrier layer. In an embodiment, the first conductive material comprises titanium tungsten and the second conductive material comprises copper. In an embodiment, the first plurality of conductive regions of the second conductive material comprise a plurality of conductive pads. In an embodiment, the first plurality of conductive regions of the second conductive material comprise a plurality of conductive traces. In an embodiment, the first plurality of conductive regions of the second conductive material comprise a plurality of conductive pads and a plurality of conductive traces. In an embodiment, the method further comprises forming a second plurality of conductive regions on at least some of the second surfaces of the first plurality of conductive regions. In an embodiment, the second plurality of conductive regions comprise the second conductive material. In an embodiment, at least some of the second plurality of conductive regions comprise redistribution layers.
In an embodiment, a semiconductor device comprises: a wafer having a plurality of die; and a first plurality of conductive regions separated by at least one dielectric region, each of the first plurality of conductive regions having: a barrier region on the wafer; and a copper region having at least a first surface on the barrier region and a second surface opposite of the first surface, wherein an oxidation thickness of the second surface of the copper region is less than 100 nanometers. In an embodiment, the first plurality of conductive regions comprise a plurality of conductive pads of a ball-grid array. In an embodiment, the oxidation thickness of the second surface of the copper region is less than 10 nanometers. In an embodiment, the first plurality of conductive regions comprise a plurality of redistribution layers and the semiconductor device further comprises: a second plurality of conductive regions on at least some of the plurality of redistribution layers. In an embodiment, the second plurality of conductive regions comprise copper bonding pads.
In the following description, certain details are set forth in order to provide a thorough understanding of various embodiments of devices, methods and articles. However, one of skill in the art will understand that other embodiments may be practiced without these details. In other instances, well-known structures and methods associated with, for example, substrates, integrated circuits, wafer level packaging, embedded wafer level packaging, ball grid arrays, embedded wafer level ball grid arrays, die, and fabrication processes, such as salicide processes, alloy deposition processes, thermal treatment processes, etching, annealing, film deposition and removal, processors, etc., have not been shown or described in detail in some figures to avoid unnecessarily obscuring descriptions of the embodiments.
Unless the context requires otherwise, throughout the specification and claims which follow, the word “comprise” and variations thereof, such as “comprising,” and “comprises,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”
Reference throughout this specification to “one embodiment,” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment,” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment, or to all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain further embodiments.
The headings are provided for convenience only, and do not interpret the scope or meaning of this disclosure or the claims.
The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not necessarily intended to convey any information regarding the actual shape of particular elements, and have been selected solely for ease of recognition in the drawings. Geometric references are not intended to refer to ideal embodiments. For example, a rectilinear-shaped feature or element does not mean that a feature or element has a geometrically perfect rectilinear shape.
The etching processes used to etch the barrier layer 124, whether performed after or at least partially simultaneously with etching of the conductive layer, can leave traces of the etchant of the barrier layer and byproducts thereof on surfaces of the die 100 which may directly or indirectly contribute to oxidation or contamination of surfaces 132 of the plurality of conductive pads 128. For example, traces of an etchant, such as hydrogen peroxide used to etch the barrier layer 124 may be left on the surfaces 132 of the conductive pads 128, and may, during subsequent thermal treatment, processes, etc., disassociate and become water and O2. The O2 may react with the conductive regions, for example, with copper, to form an oxide on the surfaces 132 of the conductive regions or pads 128. For example, even though processing typically would occur in a clean room, byproducts of the barrier layer etching process can result in the formation of oxide layers, such as copper oxide, on the surfaces 132 of the pads 128 on the order of a few micrometers in thickness during subsequent processing steps.
As previously noted, multiple pads 128 may be electrically coupled to a component, such as the component 114. The pads may have a thickness on the order of, for example, 10,000 Angstroms. The etching of the conductive regions 128 after the etching of the barrier layer 124 substantially reduces the formation of oxides on the conductive regions or pads 128 during subsequent processing due to the presence of barrier layer etchant or byproducts thereof on the conductive regions or pads. While some oxidation may occur even in a clean room environment, the etching of the conductive regions to remove barrier layer etchant or byproducts thereof from the pads can reduce the formation of oxide during subsequent processing to a thickness on the order of, for example, a few nanometers or less.
Embodiments of the die 100 may be employed, for example, in wafer level packaging, embedded wafer level packaging, ball grid arrays and embedded wafer level ball grid arrays. The conductive regions, for example, may serve as conductive pads and/or traces for wafer level packaging, embedded wafer level packaging, ball grid arrays, embedded wafer level ball grid arrays, etc.
Embodiments of methods of manufacturing semiconductor devices such as die may employ additional steps, layers, regions and processes, etc., may omit steps, layers, regions, processes, etc., and may perform steps and processes in various orders. For example, photo-resist processes, stop-etch layers or regions or sacrificial layers and regions may be employed in some embodiments. In another example, in some embodiments another material may be applied to the plurality of conductive regions 128 during subsequent processing to avoid leaving the conductive regions exposed. For example, metal or metal alloys such as copper, nickel, gold, other metals and alloys, etc., may be applied to one or more or conductive regions such as conductive pads. For example, a layer of nickel, for example on the order of 300 to 800 Angstroms in thickness, and a layer of gold, on the order of 30 Angstroms in thickness, may be applied to the conductive regions or pads 128 in some embodiments. In another example, solder balls may be applied to one or more conductive regions, such as copper pads, etc., and may be applied after the application of additional layers to the conductive regions 128. In another example, additional conductive regions may be formed or applied, such as one or more build-up regions and one or more redistribution layers, which may comprise, for example, copper.
Embodiments of methods of manufacturing semiconductor devices such as embedded wafer-level ball grid arrays, may employ additional steps, layers, regions and processes, etc., may omit steps, layers, regions, processes, etc., and may perform steps and processes in various orders. For example, additional photo-resist processes, additional barrier regions, stop-etch layers or regions or sacrificial layers and regions may be employed in some embodiments. In another example, in some embodiments another material may be applied to the plurality of conductive regions during subsequent processing to avoid leaving the conductive regions exposed. For example, metal or metal alloys such as copper, nickel, gold, other metals and alloys, etc., may be applied to one or more or conductive regions such as conductive pads. For example, a layer of nickel, for example on the order of 300 to 800 Angstroms in thickness, and a layer of gold, on the order of 30 Angstroms in thickness, may be applied to the conductive regions or pads in some embodiments. In another example, solder balls may be applied to one or more conductive regions, such as copper pads, etc., and may be applied after the application of additional layers to the conductive regions.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.