Patent Application
20060138639
An integrated circuit package may route electrical signals between an integrated circuit die and a substrate to which the package is mounted. These signals often result in unwanted resonance, which may negatively affect the performance of the integrated circuit die. Decoupling capacitors may be mounted on an integrated circuit package in order to address this resonance.
Pad 50 is coupled to an electrical circuit through microvias 51, 53 and 55 and conductive traces 52, 54 and 56. In this regard, trace 56 may extend into conductive plane 32 and connect to unshown circuitry in plane 30 or on an opposite side of core 20. Similarly, pad 60 is coupled to an electrical circuit through microvias 61, 63, 65 and 67 and conductive traces 62, 64, 66 and 68. Conventional decoupling capacitors such as capacitor 70 may exhibit an Equivalent Series Resistance (ESR) that is unsuitable for some applications. For example, the ESR of a capacitor may be too low to satisfactorily dampen the aforementioned resonance.
Integrated circuit package 100 includes core 110. Core 110 may be composed of any suitable material according to some embodiments, including but not limited to bismalemide triazine (BT) and FR4. Core 110 supports layers of conductive planes 120 through 126 that include conductive paths, or traces, for routing signals within integrated circuit package 100. The conductive traces may comprise copper or any other suitable conductive material.
Planes 120 through 126 are separated from one another by layers 130 through 136. Layers 130 through 136 may be composed of dielectric material and/or other material such as BT or FR4.
Conductive pads 140 and 150 may be suited to receive terminals of a capacitor (not shown). Conductive pads 140 and 150 electrically couple the capacitor to conductive elements of package 100. Conductive pads 140 and 150 may comprise metal-plated built-up pads, solder balls, or any conductive structure compatible with terminals to be received.
Conductive network 160 may be used to couple capacitor pad 150 to specific circuitry of package 100 and, in turn, to external circuitry and/or an integrated circuit die. Conductive network 160 includes microvia 161 within dielectric material layer 130. Generally, a microvia may electrically couple conductive elements that are disposed in different conductive planes of an integrated circuit package. Microvia 161 couples conductive pad 150 to conductive trace 162 of conductive plane 120.
Conductive trace 162 may or may not be electrically coupled to other conductive traces or elements within conductive plane 120. As shown in
An electrical signal passing through elements 161, 162, 163 and 164 returns to conductive plane 120 through microvia 165. Microvia 165 is coupled to conductive trace 166 of plane 120, which is in turn coupled to microvia 167. Microvia 167 is also coupled to conductive trace 168 of plane 122. Conductive trace 168 may extend into conductive plane 122 and be coupled to other planes within integrated circuit package 100 which eventually connect to external circuitry and/or to an integrated circuit die coupled to package 100.
Network 160 may effectively increase the ESR of a capacitor coupled to conductive pads 140 and 150. The increased ESR may reduce resonance during operation of a system including package 100. According to some embodiments, network 160 may allow the use of a capacitor having a lower ESR than would be required in the absence of network 160. The individual elements of network 160 may be designed and fabricated so as to provide a particular desired ESR. In some embodiments, a majority of the additional ESR attributable to network 160 is provided by conductive traces 162, 164, 166 and 168.
Network 170 may also couple capacitor pad 140 to other circuitry. Network 170 includes microvia 171 within dielectric material layer 130. Microvia 171 couples conductive pad 140 to conductive trace 172 of conductive plane 120. Conductive trace 172 is in turn coupled to microvia 173 of layer 132. Microvia 173 is also coupled to conductive trace 174 of conductive layer plane 122. Microvia 175 is coupled to conductive trace 174 and to conductive trace 176 of plane 122. Conductive trace 176 may extend into conductive plane 134 and be coupled to other planes within integrated circuit package 100 which eventually connect to external circuitry and/or to an integrated circuit die.
Some embodiments include one or more additional conductive pads for receiving additional terminals of a capacitor that is coupled to pads 140 and 150. Any of the one or more additional conductive pads may be coupled to a network such as network 160 or network 170.
Conductive pads 240 and 250 are for electrically coupling terminals of a capacitor to conductive elements of package 200. More specifically, conductive pad 240 is coupled to conductive network 280 and conductive pad 250 is coupled to conductive network 260. Networks 260 and 280 may be designed and fabricated to increase the ESR of a coupled capacitor in order to reduce resonance.
Conductive network 260 includes microvias 261, 263, 265 and 267 coupled as shown to conductive traces 262, 264, 266 and 268 so as to descend through the layers and planes of package 200. An electrical signal passing through elements 261 through 268 returns to conductive plane 224 through microvia 269. Microvia 269 is coupled to conductive trace 270 of plane 224, which is in turn coupled to microvia 271. Microvia 271 is also coupled to conductive trace 272 of plane 226. Conductive trace 272 may extend into conductive plane 226 and be coupled to other planes within integrated circuit package 200 which eventually connect to other unshown circuitry.
Conductive network 280 includes elements 281 through 286 coupled as shown so as to descend through the layers and planes of package 200. Microvia 287 is coupled to conductive trace 286 to return network 280 to conductive plane 222. Conductive trace 288 of plane 222 is coupled to microvia 287 and to microvia 289. Microvia 289 is also coupled to conductive trace 290 of plane 224, which may in turn be coupled to other circuitry.
Conductive networks 260 and 280 may effectively increase the ESR of a capacitor coupled to conductive pads 240 and 250. The increased ESR may reduce resonance during operation of a system including package 200, and/or may allow the use of a capacitor having a lower ESR than would be required in the absence of networks 260 and 280.
Initially, a first conductive plane is fabricated at 302. The first conductive plane includes a first conductive trace.
As shown, plane 420 includes conductive traces 425 and 427. Traces 425 and 427 may or may not be electrically coupled within plane 420. Moreover, conductive plane 420 may include other conductive traces, each of which may or may not be electrically coupled to traces 425 and/or 427. Plane 420 may include dielectric or other material in addition to conductive elements.
A first dielectric is fabricated upon the first conductive plane at 304. The dielectric material may be comprise a sheet of material that is simply laid upon the first conductive plane at 304, or may be fabricated thereon in any other manner.
Next, at 306, a first, second and third microvia are fabricated within the first dielectric material. The first and second microvia are coupled to the first conductive trace. Microvias 431, 433 and 435 of
A second conductive plane including second and third conductive traces is fabricated above the first dielectric material at 308. The second and third conductive traces are coupled to the first and second microvias, as illustrated by plane 440 and traces 442 and 444 of
A second dielectric material is fabricated upon the second conductive plane at 310, and a fourth microvia is fabricated within the second dielectric material at 312.
At 314, a first conductive pad is fabricated. Conductive pad 460 is shown in
Pins 550 of package 500 are disposed around recess 560, and conductive pad sets 561 through 568 are disposed within recess 560. Each of conductive pad sets 561 through 568 comprises two conductive pads to receive a decoupling capacitor. The conductive pads of contact sets 561 through 568 may comprise any currently- or hereafter-known conductive contacts, including but not limited to gold and/or nickel-plated copper contacts fabricated upon integrated circuit package 500. Pad sets 561 through 568 may be recessed under, flush with, or extending above the illustrated surface of package 500.
According to some embodiments, pad sets 561 through 568 are coupled to a power delivery circuit of package 500. Decoupling capacitors may be mounted in recess 560 to reduce resonance between integrated circuit package 500 and a board such as motherboard on which integrated circuit package 500 is to be mounted.
Capacitors 1010 through 1040 are mounted on package 500. Terminals of capacitors 1010 through 1040 may be mounted using surface mount techniques on conductive pads of package 500. One or more of the conductive pads may be coupled to a network of microvias and conductive traces according to some embodiments. Capacitors 1010 through 1040 may be similar to or different from one another, and each may comprise two or more capacitor terminals.
Pins 550 couple package 500 to motherboard 800. In this regard, package 500 and pins 550 may comprise a grid array to interface with a socket (not shown) of motherboard 800. According to some embodiments, package 500 is a surface-mountable substrate such as an Organic Land Grid Array substrate that may be mounted directly on motherboard 800 or mounted on a pinned interposer which mates with a socket of motherboard 800. Packaging systems other than those mentioned above may be used in conjunction with some embodiments.
Integrated circuit 700 may communicate with memory 900 through package 500 and motherboard 800. Memory 900 may comprise any type of memory for storing data, including but not limited to a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, or a Programmable Read Only Memory.
The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
