Patent Application
20240332194
The present application relates to semiconductor technology, and more particularly to an electronic device that includes a chip module assembly.
In a typical multi-chip integrated circuit, interposers may be used to electrically connect the semiconductor chips to a substrate. In other words, the semiconductor chips can communicate with one another via the substrate. However, the bandwidth of the substrate is limited. Therefore, there is a need for a structure (and a method for forming the same) in which more communication channels between the semiconductor chips are provided.
An electronic device is provided that includes a chip module assembly. The chip module assembly permits connection between two of more stacked semiconductor chips through first level semiconductor chips and one or more bridge dies that are joined on top of the first level semiconductor chips.
In one aspect of the present application, an electronic device is provided. In one embodiment, the electronic device includes a chip module assembly attached to a laminate. The chip module assembly includes at least one first semiconductor chip pair located at a first chip level, a bridge die interconnecting the at least one first semiconductor chip pair, and at least one second semiconductor chip pair located on top of the first chip level, wherein the at least one second chip pair are connected to each other through the at least one first semiconductor chip pair and the bridge die.
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Reference is first made to
The first fixture 10 can be composed of well-known materials. In some embodiments, the first fixture 10 is composed of a semiconductor material having semiconducting properties. In one example, the first fixture 10 is composed of silicon or a silicon germanium alloy. In other embodiments, the first fixture 10 can be composed of a dielectric material such as, for example, silicon dioxide, silicon nitride or silicon oxynitride. In yet other embodiments, the first fixture 10 can be composed of a metal such as, for example, copper or aluminum. Embodiments are contemplated in which the first fixture 10 includes a multilayered stack. The multilayered stack that can provide the first fixture 10 can include any combination of semiconductor materials, dielectric materials and/or metals. In one example, a multilayered stack of silicon and silicon dioxide can be used as the first fixture 10. In other embodiments, the first fixture 10 is composed of a plastic or ceramic.
Each bridge die 12 that is embedded in the first fixture 10 includes a semiconductor material, such as, for example, silicon, which contains wiring structures (metal via and/or metal lines) embedded therein. The wiring structures are composed of an electrically conductive metal or an electrically conductive metal alloy. Exemplary electrically conductive materials (i.e., metals or metal alloys) that can be use as the wiring structures include, but are not limited, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt) and alloys of Cu—Al. Each bridge die 12 can be rectangular in shape and can have a dimension of 1 mm to 5 mm by 1 mm to 5 mm.
In some embodiments, a diffusion barrier liner can be formed along a sidewall and bottom wall of the wiring structures. Exemplary diffusion barrier materials include, but are not limited to, titanium (It), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbide (WC), an alloy thereof, or a stack thereof such as Ti/TiN and Ti/WC.
The wiring structures that are present in each bridge die 12 can be formed utilizing well-known metallization processes. The metallization process can include forming openings (lines and/or vias) in the semiconductor material and thereafter filling the openings with one of the above mentioned electrically conductive metals or electrically conductive metal alloys. The filling can include any suitable deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or sputtering. A planarization process such as, for example, chemical mechanical polishing (CMP) can be performed after deposition of the electrically conductive material. In case in which a diffusion barrier liner is present, the metallization process mentioned above includes a step of forming a diffusion barrier material layer prior to filling the openings with an electrically conductive material. At least one of the wiring structures that is present in the semiconductor material that provides the bridge die 12 extends from a topmost surface of the semiconductor material to a bottommost surface of the semiconductor material. The wiring structure that extend from a topmost surface to a bottommost surface of the bridge die 12 can be referred to herein as through silicon via (TSV) structure.
The exemplary structure shown in
Referring now to
Each first semiconductor chip that provides the first semiconductor chip pairs X1-X2 has a first size and a first thickness. In one example, the first size of each first semiconductor chip that provides each first semiconductor chip pair X1-X2 is from 15 nm to 20 mm, and the first thickness for each first semiconductor chip that provides each first semiconductor chip pair X1-X2 is from 50 μm to 100 μm.
Each first semiconductor chips that provides the first semiconductor chip pairs X1-X2 includes a front-end-of-the line (FEOL) level that contains one or more semiconductor devices such as, for example, transistors located on a frontside of a wafer, a middle-of-the-line (MOL) level that includes a MOL dielectric containing a plurality of frontside contact structures embedded therein, and a back-end-of-the-line (BEOL) level that includes one or more interconnect dielectric layers having electrically conductive wiring structures embedded therein. Each first semiconductor chip that provides the first semiconductor chip pairs X1-X2 can also include backside power rails and a backside power distribution network located on a backside of the wafer. The backside of the wafer is further from the MOL or BEOL than is the frontside of the wafer. Each first semiconductor chip that provides the first semiconductor chip pairs X1-X2 that can be employed in the present application can be formed utilizing FEOL, MOL, BEOL, and backside wafer processing techniques that are well-known to those skilled in the art. At least one of the first semiconductor chips that provide the first semiconductor chip pairs X1-X2 includes a through silicon via, TSV, structure. The TSV structure present in at least one of the first semiconductor chips extends entirely throughout the chip so as to permit electrical contact with semiconductor chips that are formed thereon.
Each first semiconductor chip that provides the first semiconductor chip pairs X1-X2 includes metal bond pads (not specifically shown). The metal bond pads are formed on the uppermost surface and/or bottommost surface of each first semiconductor chip that provides the first semiconductor chip pairs X1-X2. The metal bond pads are composed of copper or any other like metal bond pad material. The metal bond pads can be formed utilizing techniques that are well-known in the art. The metal bond pads can be formed, for example, by deposition (CVD, PECVD, ALD, plating, sputtering, etc.) of the metal bond pad material (e.g., a layer of Cu. In some embodiments, a lithographic patterning process can follow the deposition of the metal bond pad material. A dielectric layer composed of a dielectric material such as, for example, silicon dioxide, can be located laterally adjacent to each of the metal bond pads that are present on each first semiconductor chip that provides the first semiconductor chip pairs X1-X2. In some embodiments, the dielectric layer is formed after the metal bond pads. In other embodiments, the dielectric layer is formed first, and thereafter the metal bond pads are formed into the dielectric layer utilizing a metallization process.
Referring now to
In some embodiments, the first gap fill material 14 can be composed of an underfill material; the underfill material reinforces the position of each first semiconductor chip pair X1-X2. The underfill material employed is typically an epoxy containing fillers. In other embodiments, the first gap fill material 14 can be composed of a dielectric material such as, for example, silicon dioxide, silicon nitride or silicon oxynitride. In some embodiments and when an underfill material is employed as the first gap fill material 14, the underfill material is formed into the gap using any gap filling process. The structure is then heated to a temperature (such as, for example, 125° C. to 180° C.) to flow the underfill material. This temperature is held until the underfill material is cured. In some embodiments and when the dielectric material is employed as the first gap fill material 14, the dielectric material can be formed by a deposition process such as, for example, CVD, PECVD, ALD, or physical vapor deposition (PVD). In some embodiments, a planarization process such as, for example, CMP, can follow the coating or deposition process.
Referring now to
The first semiconductor chip pair X1-X2 can be removed from the first fixture 12 by hand or mechanical means and placed upside down in second fixture 18. In some embodiments, more than one first semiconductor chip pair X1-X2 can be removed from the first fixture 10 and placed in the second fixture 18. Second fixture 18 includes at least one recessed region that can house the removed first semiconductor chip pair X1-X2. The second fixture 18 includes materials as mentioned above for the first fixture 10. The at least one recessed region can be formed by techniques well known to those skilled in the art.
Next, a plurality of second semiconductor chips including at least one second semiconductor pair Y1-Y2 is formed on a surface of each first semiconductor chip pair, X1-X2 that is present in the second fixture 18. Each second semiconductor chip that provides the second semiconductor chip pairs Y1-Y2 has a second size and a second thickness. In one embodiment of the present application, the second size can be less than the first size, and the second thickness can be greater than the first thickness. In one example, the second size of each second semiconductor chips that provides the second semiconductor chip pairs Y1-Y2 is from 10 mm to 12 mm, and the second thickness for each second semiconductor chips that provides the second semiconductor chip pairs Y1-Y2 is from 100 μm to 785 μm.
Each second semiconductor chip that provides the second semiconductor chip pairs Y1-Y2 includes a FEOL as defined above, a MOL level as defined above, and a BEOL as defined above. Each second semiconductor chip that provides the second semiconductor chip pairs Y1-Y2 can also include backside power rails and a backside power distribution network located on a backside of the wafer. Each second semiconductor chip that provides the first semiconductor chip pairs Y1-Y2 that can be employed in the present application can be formed utilizing FEOL, MOL, BEOL, and backside wafer processing techniques that are well-known to those skilled in the art. Each second semiconductor chip that provides the second semiconductor chip pairs Y1-Y2 includes metal bond pads as defined above (not specifically shown).
In accordance with the present application, the forming of the second semiconductor pair Y1-Y2 on first semiconductor chip pair. X1-X2 includes aligning the metal bond pads that are present on the second semiconductor chip pair Y1-Y2 with the metal bond pads that are present on the first semiconductor chip pair X1-X2, intimately contacting the aligned metal bond pads of the first semiconductor chip pair X1-X2 and the second semiconductor chip pair Y1-Y2, and bonding the aligned and contacting metal bond pads of the first semiconductor chip pair X1-X2 and the second semiconductor chip pair Y1-Y2 together. Bonding is performed at a bonding temperature that causes metal bond pad to metal bond pad bonding. In one embodiment, the bonding temperature can for a Cu—Cu bond. In one example, the bonding temperature can be from 350° C. to 400° C. Bonding can be formed with the aid an external force or pressure on the contacted first semiconductor chip pair, X1-X2 and the second semiconductor chip pair Y1-Y2. As is illustrated in
The second gap fill material 16 completely fills in the gap that is present between the second semiconductor chips of the second semiconductor chip pair Y1-Y2. The second gap fill material 16 is formed a sidewall of one of the second semiconductor chips, e.g., Y1, of the second semiconductor chip pair Y1-Y2, and on a facing sidewall of another of the second semiconductor chip, e.g., YX2, of the second semiconductor chip pair Y1-Y2. The second gap fill material 16 is formed on top of and along the sidewalls of the bridge die 12. The second gap fill material 16 typically has a topmost surface that is coplanar with a topmost surface of the second semiconductor chips of the second semiconductor chip pair Y1-Y2. The bottommost surface of the second gap fill material 16 is coplanar with a bottommost surface of the second semiconductor chips of the second semiconductor chip pair Y1-Y2.
The second gap fill material 16 can be composed of one of the materials (i.e., underfill epoxies or dielectric material) mentioned above for the first gap fill material 14. The material that provides the second gap fill material 16 can be compositionally the same as, or compositionally different from, the material that provides the first gap fill material 14. The second gap fill material 16 can be formed utilizing one of the techniques mentioned above in forming the first gap fill material 14. In some embodiments, a planarization process such as, for example, CMP, or a mold back-grinding process can follow the coating or deposition process.
As shown in
As mentioned above, the second semiconductor pair Y1-Y2 is bonded on the first semiconductor chip pair, X1-X2 such that second semiconductor chip Y1 of the second semiconductor chip pair Y1-Y2 is bonded to first semiconductor chip X2 of the first semiconductor chip pair X1-X2, and second semiconductor chip Y2 of the second semiconductor chip pair Y1-Y2 is bonded to the first semiconductor chip X1 of the first semiconductor chip pair X1-X2. Bridge die 12 directly connects the first semiconductor chip pair X1-X2 together, and indirectly connects the second semiconductor chip pair Y1-Y2 together; bridge die 12 is spaced apart from each second semiconductor chip of the second semiconductor chip pair Y1-Y2. Notably, second semiconductor chip Y1 is connected to second semiconductor chip Y2 via the first semiconductor chip X2, the bridge die 12 and the second semiconductor chip X1. Note that a metal bond pad bonding interface (e.g., Cu—Cu bonding interface) exists between the first semiconductor chip pair X1-X2 and the second semiconductor chip pair Y1-Y2. This metal-to-metal bond pad interface, i.e., Cu—Cu bonded interface, enables very tight coupling between the first semiconductor chips and the second semiconductor chips, which provides very high bandwidth data transmission between the first semiconductor chips and the second semiconductor chips; further this data transmission comes at a very low energy cost (<<1 picoJoule/bit). The Cu—Cu bonds are in a dielectric material, and are therefore insulated from other Cu—Cu bonds.
Referring now to
Referring now to
Referring now
In some embodiments, the laminate 24 is double-sided, while in other embodiments laminate 24 is multilayered. The laminate 24 is composed of a material or stack of materials that are well-known to those skilled in semiconductor packaging. In one embodiment, the laminate 24 is a printed circuit board.
In the present application, bonding includes removing the chip module assembly containing solder balls 22 from the third fixture 20. The solder balls 22 on the removed chip module assembly are aligned with metal bond pads (not shown) on the laminate 24, and then the aligned chip module assembly and laminate 24 are brought into intimate contact with each other. An external force or pressure may be applied during the contacting and remain during the heating step. The contacted chip module assembly and laminate 24 are then heated to a bonding temperature to cause bonding between the solder balls 22 and the metal bond pads present on the laminate 24. In one example, the bonding temperature can be from 217° C. to 260° C.
The underfill material 26 is then in the gap between the two bonded structures utilizing any gap filling process. The bonded structures including the underfill material 26 are then heated to a temperature (for example, 125° C. to 180° C. to flow the underfill material. Capillary action then takes over to absorb the underfill under the chip. This temperature is held until the underfill is cured.
Referring now to
Notably,
In the embodiments mentioned above, the first semiconductor chips that provide the first semiconductor chip pair X1-X2 can be logic chips, while the second semiconductor chips that provide the second semiconductor chip pair can be memory chips. In some embodiments, the memory chips can be last level cache memory chips. In such embodiments, the logic chips have a direct access to the last level cache memory chips.
In the embodiments mentioned above, the first semiconductor chips that provide the first semiconductor chip pair X1-X2 can be logic chips, while the second semiconductor chips that provide the second semiconductor chip pair can also be logic chips.
In the embodiments mentioned above, the chip module assembly of the present application has inter-stack connectivity through the bridge chip 12.
In the embodiments mentioned above, the semiconductor die 12 can contain bridge memory, and the second semiconductor chip pair Y1-Y2 can gain access to this bridge memory with short semiconductor based paths. In such embodiments, the chip module assembly can be made using a scratchpad memory or other memory.
It is noted that although the present application describes embodiments in which the bridge die 12 is formed initially with the first semiconductor chip pair X1-X2, embodiments are contemplated in which the bridge die 12 is formed after placing the removed first semiconductor chip pair X1-X2 upside down in a second fixture 18, and before forming the plurality of second semiconductor chips including at least one second semiconductor pair Y1-Y2 on a surface of each first semiconductor chip pair, X1-X2. Also, and in other embodiments, the bridge die 12 can be formed after semiconductor chip stacking.
In any of the embodiments described above, at least one other semiconductor chip pair can be located between the first semiconductor chip pair X1-X2 and the second semiconductor chip pair Y1-Y2. In some embodiments, the at least one other semiconductor chip pair can have a same dimension and/or thickness as the first semiconductor chips that provide the first semiconductor chip pair X1-X2. In some embodiments, the at least one other semiconductor chip pair can include a bridge as described above connecting the semiconductor chips that provide the at least one other semiconductor chip pair. In other embodiments, the semiconductor chips that provide the at least one other semiconductor chip pair lack any bridge die.
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
