Claims
- 1. A method for reducing electromagnetic interference in a power module, comprising:
electrically connecting a high frequency, low impedance network to at least one of a positive conducting layer in a substrate or a negative conducting layer in a substrate; and electrically connecting the high frequency, low impedance network to a ground.
- 2. The method of claim 1, wherein the high frequency, low impedance network is a surface mount capacitor.
- 3. The method of claim 2, wherein said electrically connecting the high frequency, low impedance network to a ground further comprises:
electrically connecting the surface mount capacitor or to a via connection; and electrically connecting the via connection to a ground layer in a substrate.
- 4. The method of claim 1, wherein said electrically connecting the capacitor to a ground further comprises:
soldering the capacitor to an electrically isolated substrate layer; and wire bonding the electrically isolated substrate layer to a ground connection in a power module.
- 5. A device for reducing electromagnetic interference in a power module, comprising:
a surface mount capacitor; a first electrical connection from said surface mount capacitor to at least one of a positive conducting layer in a high side substrate of a power module or a negative conducting layer in a low side substrate of a power module; and a second electrical connection from said surface mount capacitor to ground.
- 6. The device of claim 5, wherein said first electrical connection further comprises a soldered connection.
- 7. The device of claim 5, wherein said second electrical connection further comprises:
a via connection from said surface mount capacitor to an electrically grounded layer in a power module.
- 8. The device of claim 5, wherein said second electrical connection further comprises:
an electrically isolated substrate layer soldered to said capacitor; a wire bond from said electrically isolated substrate layer to a ground connection in a power module.
- 9. The device of claim 5, wherein said surface mount capacitor includes a capacitance of between about 1 and about 100 nano Farads.
- 10. A power module for reducing inductance, comprising:
a lead frame for supporting the module and for providing interconnections to the motor and power source; a substrate connected to said lead frame comprising a high side substrate and a low side substrate; high side switches proximate to said high side substrate; low side switches proximate to said low side substrate; a positive conducting layer in said high side substrate of the power module configured for connection to a positive bus; a negative conducting layer in said low side substrate of the power module configured for connection to a negative bus; and a high frequency, low impedance network electrically connected to at least one of said positive conducting layer or said negative conducting layer.
- 11. The power module of claim 10, wherein said high frequency, low impedance network further comprises a ground.
- 12. The power module of claim 10, wherein said high frequency, low impedance network is a surface mount capacitor.
- 13. The power module of claim 11, wherein said high frequency, low impedance network is a surface mount capacitor.
- 14. The power module of claim 13, wherein said ground further comprises:
a via connection electrically connected to said capacitor; and a ground layer in said substrate electrically connected to said via.
- 15. The power module of claim 13, wherein said ground further comprises:
an electrically isolated layer in said substrate; a grounded area in said lead frame; and a wire bond from said electrically isolated layer in said substrate to said ground connection mounted in said lead frame
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to and claims priority to U.S. Provisional Application No. 60/233,995, filed Sep. 20, 2000, and entitled, “Leadframe-Based Module DC Bus Design to Reduce Module Inductance,” U.S. Provisional Application No. 60/233,996, filed Sep. 20, 2000, and entitled, “Substrate-Level DC Bus Design to Reduce Module Inductance,” U.S. Provisional Application No. 60/233,993, filed Sep. 20, 2000, and entitled, “EMI Reduction in Power Modules Through the Use of Integrated Capacitors on the Substrate Level,” U.S. Provisional Application No. 60/233,992, filed Sep. 20, 2000, and entitled, “Press (Non-Soldered) Contacts for High Electrical Connections in Power Modules,” and U.S. Provisional Application No. 60/233,994, filed Sep. 20, 2000, and entitled, “Both-Side Solderable Power Devices to Reduce Electrical Interconnects.” Each of the above applications is hereby incorporated by reference herein in its entirety.
Provisional Applications (5)
|
Number |
Date |
Country |
|
60233995 |
Sep 2000 |
US |
|
60233996 |
Sep 2000 |
US |
|
60233993 |
Sep 2000 |
US |
|
60233992 |
Sep 2000 |
US |
|
60233994 |
Sep 2000 |
US |