Patent Application
20230317673
This relates generally to packaging electronic devices, and more particularly to assembling flip chip packaged semiconductor devices.
Processes for producing packaged semiconductor devices include mounting the semiconductor devices to a package substrate, and then covering the electronic devices with a mold compound in a molding process to form packages. When semiconductor devices are mounted on package substrates in flip chip packages, a semiconductor die has interconnects that extend from a proximal end placed on bond pads on a device side surface of the semiconductor die to a distal end. In a flip chip package, the semiconductor die is mounted with the device side surface facing a package substrate. The interconnects can include a conductive post connect with a proximate end on the bond pad and distal end facing away from the bond pad, and solder such as a solder ball or solder bump on the distal end of the post connect. In alternatives, the interconnects can include a conductive adhesive, or in another example, a metal to metal bond can be formed between the post connect and a metal land. In an example using solder bumps, when the semiconductor die is flip chip mounted to the package substrate, the solder bumps at the distal end of the post connects are subjected to a thermal reflow process so that the solder melts and flows to form solder joints. The solder joints mechanically attach and electrically couple the semiconductor die to the package substrate. The solder joints attach the conductive post connects to conductive areas on the package substrate. The package substrate provides terminals for the packaged device, for example ball grid array (BGA) balls. The packaged semiconductor device can then be mounted to a circuit board or module for use.
As the size and number of connections increase, and as semiconductor dies decrease in size, the pitch distance measured from center to center among the conductive post connects decreases. For some example dies, the largest pitch that allows all the interconnects to be placed on the die is smaller than the smallest pitch distance available for fabrication or assembly. The pitch requirements for the fabrication and assembly using solder bumps can be due to processing limitations in forming the post connects and solder bumps, including critical dimension requirements due to photolithography limitations, or can be due to minimum pitch limitations in the assembly process. To meet the spacing requirements for the post connect locations on the package substrate, the size of the semiconductor die may be increased to a size greater than the die area needed to fabricate the circuitry on the semiconductor die, so that the bond pads on the semiconductor die are spaced apart enough to provide the needed spacing for the post connect and solder bump processes. Because larger silicon dies reduce the number of dies made on a single wafer, the costs per die substantially increase when die area is increased. A flip chip package assembly that enables the use of smaller silicon dies is needed to increase integration and reduce costs per device.
A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board. The reconstituted semiconductor device further includes: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance of less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts, unless otherwise indicated. The figures are not necessarily drawn to scale.
Elements are described herein as “coupled.” The term “coupled” includes elements that are directly connected and elements that are indirectly connected, and elements that are electrically connected even with intervening elements or wires are coupled.
The term “semiconductor die” is used herein. As used herein, a semiconductor die can be a discrete semiconductor device such as a bipolar transistor, a few discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die can be an integrated circuit with multiple semiconductor devices such as the multiple capacitors in an A/D converter. The semiconductor die can include passive devices such as resistors, inductors, filters, or active devices such as transistors. The semiconductor die can be an integrated circuit with hundreds or thousands of transistors coupled to form a functional circuit, for example a microprocessor or memory device. The semiconductor die can be a passive device such as a sensor, example sensors include photocells, transducers, and charge coupled devices (CCDs), or can be a micro electro-mechanical system (MEMS) device, such as a digital micromirror device (DMD). The semiconductor die includes a semiconductor substrate that has a device side surface and an opposite backside surface. Semiconductor processes form devices on the device side surface of the semiconductor die.
The term “packaged semiconductor device” is used herein. A packaged semiconductor device has at least one semiconductor die electronically coupled to terminals and can have a package body that protects and covers the semiconductor die, although in some device packages the backside of the semiconductor die is exposed. In some arrangements, multiple semiconductor dies can be packaged together. For example, a power metal oxide semiconductor (MOS) field effect transistor (FET) semiconductor die and a logic semiconductor die (such as a gate driver die or controller device die) can be packaged together to from a single packaged electronic device. Additional components such as passives can be included in the packaged electronic device. The semiconductor die is mounted to a package substrate that provides conductive leads, a portion of the conductive leads form the terminals for the packaged electronic device. The semiconductor die can be flip chip mounted with the device side surface facing a package substrate surface, and the semiconductor die mounted to the leads of the package substrate by conductive post connects attached to the package substrate by solder such as solder balls or bumps. The packaged electronic device can have a package body formed by a thermoset epoxy resin in a molding process, or by the use of epoxy, plastics, resins that are liquid at room temperature and are subsequently cured, or by use of a laminated film. The package body could be formed using an additive manufacturing process with sequential material deposition or a drop on demand process. The package body may provide a hermetic package for the packaged electronic device. The package body may be formed in a mold using an encapsulation process, however, a portion of the leads of the package substrate are not covered during encapsulation, these exposed lead portions provide the exposed terminals for the packaged electronic device.
The term “package substrate” is used herein. A package substrate is a substrate arranged to receive a semiconductor die and to support the semiconductor die in a completed semiconductor package. Package substrates can include conductive lead frames, which can be formed from copper, aluminum, stainless steel and alloys such as Alloy 42 and copper alloys. For flip chip packages, a portion of the leads are arranged to receive solder joints between the leads and the conductive post connects for the semiconductor die. The solder joints form the physical die attach and the electrical connection to the package substrate. When lead frames are used as package substrates, the lead frames can be provided in strips or arrays. Dies can be placed on the strips or arrays, the dies flip chip mounted to the lead frames and the lead frames and dies then covered with mold compound in a molding process.
Alternative package substrates include pre-molded lead frames (PMLF) and molded interconnect substrates (MIS) for receiving semiconductor dies. Routable lead frames, which include multiple levels of conductors in dielectric material, can be used. These package substrates can include dielectrics such as liquid crystal polymer (LCP) or mold compound, and can include one or more layers of conductive portions in the dielectrics. Repeated plating and patterning can form multiple layers of conductors spaced by dielectrics, and conductive vias connecting the conductor layers through the dielectrics, the dielectrics can be mold compound. The package substrates can include lead frames, and can include plated, stamped and partially etched lead frames. In a partially etched lead frame, two levels of metal can be formed by etching a pattern from one side of a metal substrate configured for lead frames, and then etching from the other side, to form full thickness and partial thickness portions, and in some areas, all of the metal can be etched through to form openings through the partial etch lead frames. The package substrate can also be tape-based and film-based, and these can form substrates carrying conductors. Ceramic substrates, laminate substrates with multiple layers of conductors and insulator layers; and printed circuit board substrates of ceramic, fiberglass or resin, or glass reinforced epoxy substrates such as flame retardant 4 (FR4) can be used as the package substrates.
The term “post connect” is used herein. As used herein, a post connect is a structure made of a conductive material, for example copper or copper alloys, gold or gold alloys, or combinations of conductive metal that provides a connection between a semiconductor die and a package substrate. A proximal end of the post connects is mounted to a bond pad on the device side surface of a semiconductor die, while a distal end of the post connect is extended away from the bond pad of the semiconductor die. When the packaged semiconductor device is oriented with the semiconductor die positioned over and facing a die mount surface of a package substrate in a flip chip orientation, the post connect makes a vertical connection between a conductive portion of the package substrate and the bond pad of the semiconductor die. Some references describe a type of post connect as a “controlled collapse chip connection” or as “C4” bumps. The conductive post connect includes a post of conductor material and has a distal end facing away from the surface of the bond pad on the semiconductor die, where a proximal end of the post connect is mounted to the bond pad.
A package substrate, such as a lead frame, molded interconnect substrate (MIS), premolded lead frame (PMLF) or multilayer package substrate, has conductive portions on a planar die side surface. Leads of a metal lead frame are conductive all along the surfaces, while for other substrate types, conductive lands in dielectric substrate material are arranged and aligned to electrically and mechanically connect to the conductive post connects. The post connects can extend along the same direction as a conductive lead in the package substrate, so that the post connect appears as a rail or has a rectangular cross section. When the post connect is copper and is pillar shaped and has solder bumped at the end, it may be referred to as a “copper pillar bump.” A copper pillar bump or copper bump is therefore an example of a post connect. In addition to the pillar shape, the post connect can also be a column, rectangle or rail shape, and can have an oval, round, square or rectangular cross section. In examples, multiple post connects can be arranged in parallel to one another with additional post connects coupled to a common trace on a package substrate, to provide a low resistance path between the semiconductor die and the package substrate. A thermal reflow process is used to melt solder between the post connect and the package substrate to make a solder joint. The solder joint provides both a mechanical attachment and an electrical connection between the semiconductor die and the package substrate. Post connects are used to form several, tens, hundreds or thousands of connections between a semiconductor die and a package substrate in fine pitch semiconductor packages. As device sizes continue to fall and the density of connections rises, these sizes may decrease. Spacing between post connects may also decrease.
In packaging semiconductor devices, a mold compound may be used to partially cover a package substrate, to cover a semiconductor die, and to cover the connections from the semiconductor die to the package substrate. This “encapsulation” process is often an injection molding process, where thermoset mold compound such as epoxy resin can be used. A room temperature solid or powder mold compound can be heated to a liquid state and then molding can be performed. Transfer molding can be used. Unit molds shaped to surround an individual device may be used, or block molding may be used, to form the packages simultaneously for several devices using molten mold compound. The devices can be provided in an array of several, hundreds or even thousands of devices in rows and columns that are molded together. After the molding, the individual packaged devices are cut from each other in a sawing operation by cutting through the mold compound and package substrate in saw streets formed between the devices. Portions of the package substrate leads are exposed from the mold compound package to form terminals for the packaged semiconductor device.
In flip chip die attach processes, solder balls, solder columns, or solder bumps are used to form solder joints between the conductive post connects and a conductive lead or land on a package substrate. The post connects are formed extending from bond pads of the semiconductor die. The semiconductor die is then oriented with the distal ends of the post connects facing a die mounting surface of a circuit board or package substrate. A solder reflow process is used to attach the post connects to conductive die pads or leads on the package substrate, the solder joints forming a physical attachment and an electrical connection between the package substrate and the semiconductor die.
The term “scribe lane” is used herein. A scribe lane is a portion of semiconductor wafer between semiconductor dies. Sometimes in related literature the term “scribe street” is used. Once semiconductor processing is finished and the semiconductor devices are complete, the semiconductor devices are separated into individual semiconductor dies by severing the semiconductor wafer along the scribe lanes. The separated dies can then be removed and handled individually for further processing including packaging. This process of removing dies from a wafer is referred to as “singulation” or sometimes referred to as “dicing.” Scribe lanes are arranged on four sides of semiconductor dies and when the dies are singulated from one another, rectangular semiconductor dies are formed.
The term “saw street” is used herein. A saw street is an area between molded electronic devices used to allow a saw, such as a mechanical blade, laser or other cutting tool to pass between the molded electronic devices to separate the devices from one another. This process is another form of singulation. When the molded electronic devices are provided in a strip with one device adjacent another device along the strip, the saw streets are parallel and normal to the length of the strip. When the molded electronic devices are provided in an array of devices in rows and columns, the saw streets include two groups of parallel saw streets, the two groups are normal to each other and so the saw will traverse the molded electronic devices in two different directions to cut apart the packaged electronic devices from one another in the array.
The term “quad flat no-lead” or “QFN” is used herein for a type of electronic device package. A QFN package has conductive leads that are coextensive with the sides of a molded package body and the leads are on four sides. Alternative flat no-lead packages may have leads on two sides or only on one side. These can be referred to as “small outline no-lead” or “SON” packages. No lead packaged electronic devices can be surface mounted to a board. Leaded packages can be used with the arrangements where the leads extend away from the package body and are shaped to form a portion for soldering to a board. A dual in line package, or DIP, can be used with the arrangements. A small outline package or SOP can be used with the arrangements.
The term “ball grid array” or “BGA” is used herein for another type of semiconductor device package. A BGA package has solder balls on a board side surface, which form the terminals of the semiconductor device package. The BGA package can be mounted to a printed circuit board by a solder reflow process to form solder joints between the BGA package and the printed circuit board. For a semiconductor device with many input and output terminals, the BGA package can have solder balls in a grid or array on the board side of the semiconductor device package.
The term “reconstituted semiconductor device” is used herein. A reconstituted semiconductor device includes a semiconductor die that is partially covered in a dielectric material, with a redistribution layer formed over the semiconductor die. In an example arrangement, the semiconductor die has bond pads at a first pitch distance, and the redistribution layer had conductors in passivation layers that couple the bond pads to conductive lands configured for a solder ball or post connect, the solder balls or post connects are at a second pitch that is larger than the first pitch distance.
In the arrangements, a semiconductor die has post connects mounted with a proximate end on bond pads on a device side surface of the semiconductor die, and having solder balls or bumps formed on a distal end of the post connects. Semiconductor dies are singulated from a semiconductor wafer. The semiconductor dies have bond pads on a device side surface with a first minimum pitch distance between the bond pads. The semiconductor dies are placed on a carrier spaced from one another. A dielectric such as a mold compound, thermoplastic, resin or epoxy is formed over a portion of the semiconductor dies to form a reconstituted wafer with the semiconductor dies having bond pads exposed from the dielectric. A redistribution layer is formed over the bond pads of the semiconductor dies, bumps or post connects are formed on the redistribution layer to form solder balls or solder bumps with a second pitch distance between them, the second pitch distance being greater than the first pitch distance. The reconstituted wafer is then singulated to form a reconstituted semiconductor device that includes the semiconductor dies and the redistribution layers with the solder bumps. The reconstituted semiconductor device is then flip chip mounted to a package substrate using a solder reflow process. The package substrate can be a ceramic circuit board, a printed circuit board of fiberglass, such as flame retardant 4 (FR4) or other dielectric, a pre-molded lead frame, a multilayer package substrate formed by additive manufacturing using plating of conductors and dielectric in layers, or another package substrate. In an example arrangement, the package substrate is a ball grid array (BGA) package substrate and has solder balls on a surface opposite a device side surface. A protective lid or a molding process can provide a protective package body to complete the packaged device. Use of the reconstituted semiconductor device with the second pitch between the bumps or solder balls enables a semiconductor die with the first smaller pitch between bond pads to be flip chip mounted in a semiconductor device package, enabling the use of smaller semiconductor dies. Use of smaller semiconductor dies, such as are increasingly produced in advanced semiconductor processes, along with the use of flip chip BGA packages, allows for reduced costs per device.
As semiconductor processes continue to advance, the minimum feature sizes that can be manufactured on a semiconductor die continue to fall. The semiconductor die sizes fall with the process node minimum feature size. Smaller semiconductor dies tend to reduce device costs, as the number of semiconductor devices produced on a single wafer increases, while the processing costs per wafer remains relatively stable, so that as the minimum feature sizes falls, and die sizes shrink, the number of dies produced per wafer increases, and the costs per completed device fall. As the semiconductor dies become smaller, the pitch between bond pads on the device side surface of the semiconductor dies also falls, in a particular example, to a bond pad pitch of less than about 60 microns. However, the processes used to form solder balls or bumps are not impacted by the semiconductor process node minimum feature size, and these processes have larger minimum pitch requirements, such as 150 microns center to center. When a semiconductor die is flip chip mounted, as is in
In the arrangements, a reconstituted semiconductor device is formed with a redistribution layer over a semiconductor die to map a first bond pad pitch on the semiconductor die to a second larger solder bump pitch for use in a flip chip package. The use of the arrangements allows smaller semiconductor dies, which are produced at lower costs, to be packaged in flip chip BGA packages.
In an example, a die size for a semiconductor device to be packaged in a flip chip BGA package was reduced by use of the arrangements from a 155 micron bond pad pitch (a pitch compatible with a solder bumping process) to a 50 micron bond pad pitch. The die size required was reduced from 3.1×3.1 millimeters to 1×1 millimeter, resulting in approximately 90% reduction in silicon die cost due to the increase number of dies per wafer. While the use of the redistribution layer over the reconstituted semiconductor device dielectric material increases the costs per packaged unit, the total cost of a packaged semiconductor device was reduced by over 60 percent, so that use of the arrangements resulted in a packaged device that costs about one third of that of a packaged device made without the use of the arrangements. This result was found for several different types of semiconductor devices made on both 8 inch and 12 inch wafers using different processes. By enabling use of smaller semiconductor dies, the arrangements decrease the overall device costs even while adding elements (the materials used in forming the reconstituted semiconductor devices of the arrangements includes a dielectric material, and a redistribution layer over the dielectric material with conductors and passivation layers).
At step 505, the method continues by forming solder bumps on the redistribution layer at a second pitch between the solder bumps that is greater than the first pitch. (See
Use of the processes and the arrangements allows a semiconductor die with a first minimum pitch between bond pads to be flip chip mounted to a package substrate using solder bumps at a second minimum pitch between solder bumps that is greater than the first bond pad pitch. In examples the first pitch distance is less than 100 microns, and can be less than 60 microns. The second pitch distance is greater than the first pitch distance and can be 100 microns, or 150 microns in examples. Use of the arrangements enables smaller die size for a flip chip semiconductor device package by use of a reconstituted semiconductor device with a redistribution layer to increase from a bond pad pitch of the semiconductor die to a greater pitch for the solder bumps.
Modifications are possible in the described arrangements, and other alternative arrangements are possible within the scope of the claims.
