The present invention relates to a flip chip package technique for attaching a die on a carrier.
For semiconductor industry field, the flip-chip technology is very popular in every kind of package devices, which is advantageous in reducing the package size and shortening of the signal conduction path.
Referring to
The flip-chip package structure 100 comprises a carrier 11, a ball bump 13, and a die 15. Wherein the carrier 11 is a lead frame or structure that comprises a lead pattern side 112, and an electrode 111 is disposed on the lead pattern side 112. Besides, the ball bump 13 is bonded to the electrode 111 of the carrier 11 by a wire ball bonding technology.
The die 15 comprises an active side 152, and a bond pad 151 is disposed on the active side 152. The bond pad 151 of the die 15 will attach on the carrier 11 through the ball bump 13, so that the die 15 and the carrier 11 joint together to form the flip chip package structure 100.
Regarding the flip-chip structure 100 of the prior art, the die 15 is attached on the carrier 11 through the ball bump 13, the ball bump 13 is formed by a wire ball bonding technology, and therefore in bumping size and shapes can only be constrained to a small round ball. So the contact area between the die 15 and the carrier 11 will be smaller, which makes the die 15 easily disconnection form the carrier 11, and further limits electrical performance and thermal dissipation performance when a lower contact resistance and a more efficient thermal dissipation are needed.
It is the primary objective of the present invention to provide a flip-chip package structure and the die attach method thereof, in which the die is attached on the carrier through a block bump of larger size, so as to increase the compactness between the die and the carrier.
It is the secondary objective of the present invention to provide a flip-chip package structure and the die attach method thereof, the block bump is easily formed into the larger sizes by a wedge bonding, which reduce the contact resistance and increase the contact area between the die and the carrier, so as to enhance the electrical performance and thermal dissipation performance of the flip-chip package structure.
To achieve the above mentioned and other objectives, the present invention provides a flip chip package structure, comprising: a carrier; a block bump formed on the carrier; and a die with a bond pad disposed thereon, wherein the bond pad of the die is bonded to the block bump of the carrier.
The present invention further provides a flip chip package structure, comprising: a carrier comprising a lead pattern side, and a first electrode pin and a second electrode pin disposed on the lead pattern side; a first block bump and a second block bump respectively bonded to the first electrode pin and the second electrode pin by ultrasonic bonding or wedge bonding such that metal diffusion is happened between the bumps and the electrode pins; and a die comprising an active side and a backside, and a first bond pad and a second bond pad disposed on the active side; wherein the first bond pad and the second bond pad of the die are respectively bonded to the first block bump and the second block bump of the carrier.
The present invention further provides a die attach method of a flip chip package structure, comprising: providing a carrier with a electrode and a die with a bond pad ; forming a block bump on the electrode; and bonding the bond pad of the die to the block bump such that the die is attached to the carrier.
Referring to
First, as shown in
As shown in
As shown in
As shown in
The block bump 23 of the present invention is formed by the wedge bonding technology, and therefore in bumping size and shapes can easily form larger bump than the ball bump (13) of the prior art, in which the die 25 is attached on the carrier 21 through a block bump 23 of larger size, so as to increase the compactness between the die 25 and the carrier 21, and avoid the die 25 disconnection form the carrier 21. Furthermore, the block bump 23 of larger size will reduce the contact resistance and increase the contact area between the die 25 and the carrier 21, so as to enhance the electrical performance and thermal dissipation performance of the flip-chip package structure 200 after it is packaged.
Referring to
The flip-chip package structure 300 of the present invention is further applied in power transistor devices wherein the flip-chip (or semiconductor die itself) in the flip-chip package structure 300 could be a power transistor chip. In one embodiment the flip-chip package structure 300 is a quad flat non-leaded package structure (QFN).
The flip-chip package structure 300 comprises a carrier 31, a first block bump 331, a second block bump 333, and die 35.
Wherein the carrier 31 is a lead frame or substrate that comprises a lead pattern side 312, a first electrode pin 311 and a second electrode pin 313 are disposed on the lead pattern side 312. The first electrode pin 311 is a source pin, and the second electrode pin 313 is a gate pin.
The first block bump 331 and the second block bump 333 are respectively bonded to the first electrode pin 311 and the second electrode pin 313 of the carrier 31 by ultrasonic bonding or wedge bonding such that metal diffusion is happened between the block bumps 331/333 and the electrode pins 311/313. The material of the first block bump 331 and the second block bump 333 is selected as an aluminum wire and ribbon, a gold wire and ribbon, or another wire and ribbon of a specific metal-type. Besides, the first block bump 331 and the second block bump 333 are respectively formed on the first electrode pin 311 and the second electrode pin 313 by a wedge bonding technology.
The die 35 comprises an active side 352 and a backside 354, a first bond pad 351 and a second bond pad 353 are disposed on the active side 352, and an electrode layer 355 is disposed on said backside 354. The first bond pad 351 is a source electrode pad (aluminum material pad), the second bond pad 353 is a gate electrode pad (aluminum material pad), the electrode layer 355 is a drain electrode layer, and the size of the first bond pad 351 is larger than the size of the second bond pad 353.
The first bond pad 351 and the second bond pad 353 of the die 35 align with the first block bump 331 and the second block bump 333, then the first bond pad 351 and the second bond pad 353 of the die 35 are respectively bonded to the first block bump 331 and the second block bump 333 of carrier 31 by thermal-sonic bonding, thermal-compress bonding, or ultrasonic-compress bonding, and further a force and/or ultrasonic vibration apply on the die 35 to make the die 35 connected with the carrier 31 compactly. Similarly, the first block bump 331 and the second block bump 333 can be formed larger size by the wedge bonding technology, which increase the compactness between the die 35 and the carrier 31, so as to avoid the die 35 disconnection form the carrier 31. Furthermore, the first block bump 331 and the second block bump 333 of larger size will reduce the contact resistance and increase the contact area between the die 35 and the carrier 31, so as to enhance the electrical performance and thermal dissipation performance of the flip-chip package structure 300 after it is packaged.
Furthermore, the first block bump 331 and the second block bump 333 of the invention can be formed on the carrier 31 by using the existing metal ribbon bonding machine, therefore don't need to modify or regulate the machine, such as to reduce the production cost.
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
This application claims priority of U.S. Provisional Application No. 61/119,046 filed on 2 Dec. 2008 under 35 U.S.C. §119(e), the entire contents of which are all hereby incorporated by reference.
Number | Date | Country | |
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61119046 | Dec 2008 | US |