Patent Application
20080191333
This invention relates to a structure of Panel level package (PLP), and more particularly to a substrate with die receiving opening to receive an Image Sensor die for PLP.
In the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on. As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip.
Furthermore, because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dice). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small dimensions combined with extremely good electrical properties.
WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
Though the advantages of WLP technique mentioned above, some issues still exist influencing the acceptance of WLP technique. For example, although utilizing WLP technique can reduce the CTE mismatch between IC and the interconnecting substrate, as the size of the device minimizes, the CTE difference between the materials of a structure of WLP becomes another critical factor to mechanical instability of the structure. Furthermore, in this wafer-level chip-scale package, a plurality of bond pads formed on the semiconductor die is redistributed through conventional redistribution processes involving a redistribution layer into a plurality of metal pads in an area array type. Solder balls are directly fused on the metal pads, which are formed in the area array type by means of the redistribution process. Typically, all of the stacked redistribution layers are formed over the built-up layer over the die. Therefore, the thickness of the package is increased. This may conflict with the demand of reducing the size of a chip.
Therefore, the present invention provides a FO-WLP structure without stacked built-up layer and RDL to reduce the package thickness to overcome the aforementioned problem and also provide the better board level reliability test of temperature cycling.
The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein terminal pads are formed under the contact through holes structure and contact pads are formed on a upper surface of the substrate. A die having a micro lens area is disposed within the die through hole by adhesion. A wire bonding is formed on the die and the substrate, wherein the wire bonding is coupled to bonding pads of the die and the contact pads of the substrate. A protective layer is formed to cover the wire bonding and fill into the gap between die edge and sidewall of die through hole to adhesive the die and substrate except the transparent cover area. A transparent cover is disposed on the die within the die through hole by adhesion to create an air gap between the transparent cover and the micro lens area. Conductive bumps are coupled to the terminal pads.
It should be noted that the present invention provide a method for forming semiconductor device, such as CMOS Image Sensor (CIS), package. Firstly, the process includes providing a substrate with a die through hole and a contact through holes structure formed there through on a tool, wherein the terminal pads are formed under said contact through holes structure and a contact pads are formed on an upper surface of said substrate. Next, an adhesive material is attached on image sensor chips back side (optional process). Subsequently, a pick and place fine alignment system is used to re-distribute known good dice image sensor chips on the tool with desired pitch. A wire bonding is formed to couple between the chip and contact pad of the substrate. Next, a protective layer is formed to cover the wire bonding and fill into the gap between the die edge and the sidewall of the die through hole, and vacuum curing then separating the tool. Finally, semiconductor device package is singulated into individual units.
The image sensor chips has been coated the protection layer (film) on the micro lens area; the protection layer (film) with the properties of water repellent and oil repellent that can away the particles contamination on the micro lens area; the thickness of protection layer (film) preferably around 0.1 um to 0.3 um and the reflection index close to air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed in silicon wafer form. The materials of protection layer can be SiO2, Al2O3 or Fluoro-polymer etc.
The material of the substrate includes organic epoxy type FR4, FR5, BT, PCB (print circuit board), alloy or metal. The alloy includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). Alternatively, the substrate could be glass, ceramic or silicon.
a˜3d illustrate process steps for making CIS chips with protection transparent cover for the panel wafer form (cross section).
a˜4e illustrate process steps for making CIS chips with protection transparent cover for the panel wafer form (cross section) according to another embodiment of the present invention.
a˜5f illustrate process steps for making panel level CIS chip scale package with protection transparent cover for the panel form (cross section).
The invention will now be described in greater detail with preferred embodiments of the invention and illustrations attached. Nevertheless, it should be recognized that the preferred embodiments of the invention is only for illustrating. Besides the preferred embodiment mentioned here, present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying Claims.
The present invention discloses a structure of Panel Level Package (PLP) utilizing a substrate having predetermined die through holes and contact (inter-connecting) through holes formed, and the contact metal pads on the upper side and the terminal metal pads on the lower side through the metal of through holes therein and a plurality of openings passing through the substrate. A wire bonding is connected between pads formed on an image sensor die and contact metal pads of the pre-formed substrate.
The die 16 is disposed within the die through hole 10 and fixed by an adhesion tape (die attached—optional process) material 14 as the protection material for the backside of die. The dimension of the width (size) of the die through hole 10 could be larger than the width (size) of the die 16 around 100 um each side. As know, contact pads (bonding pads) 20 are formed on the die 16 by a metal plating method. In one embodiment, the protective layer (liquid compound) 26 will be re-filled into gap of the through holes 10 (between die edge and the sidewall of die receiving through hole) except the die 16 area for isolation. In one embodiment, the protective layer 26 is an elastic material, photosensitive material or dielectric material. Besides, a barrier layer 32 may be formed, such as by using a metal plating method, on side wall of the substrate 2 for better adhesion with the protective layer (isolating material). Another adhesive material 38 is formed over the die 16 to create an opening 46 and adhesive the transparent cover 36 to create an air gap between the transparent cover 36 and the micro lens area 42. The wire bonding 24 is formed on the die 16, wherein the wire bonding 24 keeps electrically connected with the die 16 through the I/O pads 20 and the contact pads 22, thereby forming inter-connecting contact to contact the terminal pads 8. The aforementioned structure constructs LGA type (terminal pads in the peripheral of package) package.
It should be noted that the opening 46 is formed on the die 16 and a protection layer 40 to expose the micro lens area 42 of the die 16 for CMOS Image Sensor (CIS). The protection layer 40 can be formed over the micro lens on the micro lens area 42. The image sensor chips have been coated the protection layer (film) 40 on the micro lens area; the protection layer (film) 40 with the properties of water repellent and oil repellent that can away the particle contamination on the micro lens area. The thickness of protection layer (film) 40 is preferably around 0.1 um to 0.3 um and the reflection index close to the air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed in silicon wafer form. The materials of protection layer can be SiO2, Al2O3 or Fluoro-polymer etc.
Finally, a transparent cover 36 with coating IR filter (optionally) is formed over the micron lens area 42 for protection. The transparent cover 36 is composed of glass, quartz, etc.
An alternative embodiment can be seen in
The substrate could be rectangular type such as panel form, and the dimension could be fit into the wire bonder machine. As shown in
a˜3d illustrate process steps for making CIS chips with protection transparent cover for the panel/wafer form (cross section). As can be seen from the
a˜4e illustrate process steps for making CIS chips with protection transparent cover for the panel/wafer form (cross section) according to another embodiment of the present invention. As seen from the
a˜5f illustrate process steps for making panel level CIS chips scale package with protection transparent cover for the panel form (cross section). The process for the present invention includes providing an alignment tool (chips redistributed tool) 90 with alignment pattern formed thereon. Then, the pattern glues is printed on the tool 90 (be used for sticking the back side surface of dice), followed by using pick and place fine alignment system with die bonding function to re-distribute the known good dice on the tool with desired pitch. The pattern glues will stick the chips on the tool 90. Alternatively, a die attached tape can be used. Subsequently, a substrate 92 with die through holes 94 and contact through hole 96, and contact pad 22 on the upper side and terminal pads 8 on the lower side is provided on the tool 90, shown in
After the ball placement or solder paste printing, the heat re-flow procedure is performed to re-flow on the substrate side (for BGA type). The testing is executed. Panel level final testing is performed by using vertical probe card. After the testing, the substrate 92 is sawed along the scribe line 108 to singulate and separate the package into individual units, shown in
Referring to
Hence, the advantages of the present invention are:
The substrate is pre-prepared with pre-form through hole and wiring circuit; it can generates the super thin package due to die insert inside the substrate, thickness under 200 um (from image sensor surface); it can be used as stress buffer releasing area by filling silicone rubber or liquid compound materials to absorb the thermal stress due to the CTE difference between silicon die (CTE˜2.3) and substrate (FR5/BT−CTE—16)). The packaging throughput will be increased (manufacturing cycle time was reduced) due to apply the simple process: die bonding, wire bonding, protection layer and sawing, it is due to the lower pin count structure of image sensor chips. The terminal pads are formed on the opposite surface to the dice active surface (pre-formed). The dice placement process is the same as the current process—die bonding. No particles contamination during process to module is produced for the present invention which is put the glass cover in wafer form once it is completed at fab. The surface level of die and substrate can be the same after die is attached on the die through hole of substrate. The package is cleanable due to glass cover on the micro lens. The chip scale package has size around chip size plus 0.5 mm/side. The reliability for both package and board level is better than ever, especially, for the board level temperature cycling test, it was due to the CTE of substrate and PCB mother board are identical, so, no thermal mechanical stress be applied on the solder bumps/balls. The cost is low and the process is simple. The manufacturing process can be applied fully automatic especially in module assembly by using the SMT process. It is easy to form the combo package (dual dice package). The LGA type package has peripheral terminal pads for SMT process. It has high yield rate due to particles free, simple process, fully automation.
Although preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described preferred embodiments. Rather, various changes and modifications can be made within the spirit and scope of the present invention, as defined by the following Claims.
