Claims
- 1-47. (cancele)
- 48. A method for forming interconnects on a substrate, comprising:
providing a substrate having fine recesses in a surface of the substrate; plating a film of a conductive material on the surface of the substrate in a plating liquid; and electrolytic-etching a surface of the plated film formed on the surface of the substrate in an etching liquid.
- 49. The method according to claim 48, wherein the etching liquid contains at least one additive selected from the group consisting of an additive which forms a complex compound or an organic complex with the metal of the plate film and an additive which can lower the corrosion potential of the metal of the plated film.
- 50. The method according to claim 48, wherein a waveform of current flowing in said electrolytic-etching is a pulse waveform or a PR pulse waveform.
- 51. A method for forming interconnect on a substrate, comprising:
providing a substrate having a recess in a surface of the substrate, plating the substrate with copper to form a copper film on the surface and to fill copper into the recess of the substrate; electrolytic-polishing or chemical-polishing a surface of the copper film on the substrate in a polishing liquid; and annealing the substrate after said polishing.
- 52. The method according to claim 51, wherein the annealing the substrate is carried out in such a state that the copper film remains on the entire surface of the substrate.
- 53. The method according to claim 51, further comprising chemical-mechanical-polishing the surface of the copper film on the surface of the substrate, after said annealing.
- 54. The method according to claim 53, further comprising cap-plating the substrate to selectively cover an exposed surface of a copper interconnect with a protective film, after said chemical-mechanical-polishing.
- 55. A method for forming interconnect on a substrate, comprising:
providing a substrate having a recess in a surface of the substrate, plating the substrate with copper to form a copper film on the surface and to fill copper into the recess of the substrate; annealing the substrate having the copper film thereon; and electrolytic-polishing or chemical-polishing a surface of the copper film on the substrate in a polishing liquid, after said annealing.
- 56. The method according to claim 55, wherein the polishing is carried out to form an exposed surface of a copper interconnect.
- 57. The method according to claim 55, further comprising cap-plating the substrate to selectively cover the exposed surface of the copper interconnect with a protective film.
- 58. A method for forming interconnect on a substrate, comprising:
providing a substrate having recesses in a surface of the substrate and a copper film on the surface and in the recesses of the substrate; electrolytic-polishing or chemical-polishing a surface of the copper film on the surface of the substrate, where only copper is exposed thereon, in a first polishing liquid in which the dissolution of copper is suppressed; and electrolytic-polishing or chemical-polishing the surface of the substrate, where only copper is exposed, or copper and a conductive material other than copper are exposed, in a second polishing liquid in which the dissolution of copper is further suppressed than in a first polishing liquid.
- 59. The method according to claim 58, further comprising removing a copper remaining on the surface of said other conductive material by electrolytic-polishing or chemical-polishing.
- 60. The method according to claim 58, further comprising removing said other conductive material remaining on the surface of the substrate.
- 61. The method according to claim 60, wherein said copper on the recesses and said other conductive material remaining on the surface of the substrate is removed by passivating a surface of said copper and preferentially electrolytic-polishing or chemical-polishing said other conductive material.
- 62. The method according to claim 60, wherein said copper on the recesses and said other conductive material remaining on the surface of the substrate is removed by passivating an entire surface including said copper and said other conductive material and composite-electrolytic-polishing said entire surface.
- 63. A method for forming interconnects on a substrate, comprising:
providing a substrate having a small recess and a large recess in a surface of the substrate, wherein the surface of the substrate being covered with a seed layer; plating a film of a conductive material on a surface of the seed layer with a plating liquid to deposit the conductive material in the small recess and the large recess, said plated film having a raised portion on the small recess; and electrolytic-etching a surface of the plated film to selectively remove the raised portion on the small recess.
- 64. A method for forming interconnects on a substrate, comprising:
providing a substrate having a recess in a surface of the substrate, wherein the surface of the substrate being covered with a seed layer; plating a film of a conductive material on a surface of the seed layer with a plating liquid to deposit the conductive material in the recess, said plated film having a raised portion; forming a passivated film on a surface of said raised portion; and removing the passivated film and the plated film, selectively, of the raised portion.
- 65. A method for forming interconnects on a substrate, comprising:
providing a substrate having a recess in a surface of the substrate, wherein the surface of the substrate being covered with a seed layer; plating a film of a conductive material on a surface of the seed layer with a plating liquid to deposit the conductive material in the recess; forming a passivated film on a surface of the plated film; and removing the passivated film and the plated film while leaving the plated film on the recess of the substrate.
Priority Claims (4)
Number |
Date |
Country |
Kind |
2000-196993 |
Jun 2000 |
JP |
|
2000-356590 |
Nov 2000 |
JP |
|
2001-77154 |
Mar 2001 |
JP |
|
2001-77155 |
Mar 2001 |
JP |
|
Parent Case Info
[0001] This is a Divisional Application of U.S. patent application Ser. No. 09/891,472, filed Jun. 27, 2001.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09891472 |
Jun 2001 |
US |
Child |
10837630 |
May 2004 |
US |