Method for making QFN package with power and ground rings

Abstract

A method to manufacture a package that encases at least one integrated circuit device and the package so manufactured. The method includes the steps of (1) providing a leadframe having a die pad, leads, at least one ring circumscribing the die pad and disposed between the die pad and the leads, a plurality of tie bars projecting outwardly from the at least one ring, and at least one connecting bar electrically interconnecting and mechanically supporting the die pad to the ring; (2) affixing the at least one integrated circuit device to a first side of the die pad and electrically interconnecting the at least one integrated circuit device to the leads and to the at least one ring; (3) encapsulating the at least one integrated circuit device, the first side of the die pad and a first side of the ring in a molding resin while retaining an opposing second side of the ring external to said molding resin; and (4) severing the at least one connecting bar to electrically isolate the die pad from the ring.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a lead frame matrix of the invention in bottom planar view.

FIG. 2 is an enlarged view of a portion of the lead frame matrix of FIG. 1.

FIGS. 3A-3C show the enlarged view of FIG. 2 in cross-sectional representation along with differing leadframe configurations achieved with alternative etching procedures.

FIGS. 4A-4C show subsequent encapsulation and isolation of the leadframe configuration of FIG. 3A.

FIGS. 5A-5C show subsequent encapsulation and isolation of the leadframe configuration of FIG. 3B.

FIGS. 6A-6C show subsequent encapsulation and isolation of the leadframe configuration of FIG. 3C.

FIG. 7 shows a QFN package of the invention in bottom isometric view.

FIG. 8 shows the QFN package of the invention in top isometric view.

FIG. 9 shows the QFN package of the invention in cross-sectional representation.

Claims

1. A method to manufacture a leadframe suitable for use in a package to encapsulate one or more integrated circuit devices comprising the step of: first partially chemically etching a metallic sheet from a first side thereof to form leadframe features including a die pad, leads, at least one ring circumscribing said die pad and disposed between said die pad and said leads, and a plurality of tie bars projecting outwardly from said at least one ring.

2. The method of claim 1 including forming a first ring circumscribing said die pad and a second ring circumscribing said first ring wherein said plurality of tie bars project outwardly from said second ring and a first array of connecting bars electrically interconnect and mechanically support said die pad to said first ring and a second array of connecting bars electrically interconnect and mechanically support said first ring to said second ring.

3. The method of claim 2 wherein said members of said first array of connecting bars and members of said second array of connecting bars formed in an arrangement selected from the group consisting of staggered, aligned and combinations thereof.

4. The method of claim 2 including the additional step of second partially chemically etching said metallic sheet from an opposing second side thereof to a depth less than that required to electrically isolate said leads while retaining at least one connecting bar electrically interconnecting and mechanically supporting said die pad and said at least one ring by at least one of said plurality of tie bars.

5. A method to manufacture a package to encase at least one integrated circuit device comprising the steps of: providing a leadframe having a die pad, leads, at least one ring circumscribing said die pad and disposed between said die pad and said leads, a plurality of tie bars projecting outwardly from said at least one ring, and at least one connecting bar electrically interconnecting and mechanically supporting said die pad to said ring;affixing said at least one integrated circuit device to a first side of said die pad and electrically interconnecting said at least one integrated circuit device to said leads and to said at least one ring;encapsulating said at least one integrated circuit device, said first side of said die pad and a first side of said ring in a molding resin while retaining an opposing second side of said ring external to said molding resin; andsevering said at least one connecting bar to electrically isolate said die pad from said ring.

6. The method of claim 5 including the step of plating an opposing second side of said die pad and said opposing second side of said ring prior to said step of severing.

7. The method of claim 5 including forming a first ring circumscribing said die pad and a second ring circumscribing said first ring wherein said plurality of tie bars project outwardly from said second ring and a first array of connecting bars electrically interconnect and mechanically support said die pad to said first ring and a second array of connecting bars electrically interconnect and mechanically support said first ring to said second ring.

8. The method of claim 7 including the step of plating an opposing second side of said die pad and said opposing second sides of said first ring and said second ring prior to said step of severing.

9. The method of claim 5 including the step of disposing molding resin in a portion of said package removed during said step of severing.

10. The method of claim 5 including the step of disposing a lacquer in a portion of said package removed during said step of severing.

11. The method of claim 5 wherein said leadframe is provided as a member of an array of leadframes and said members are singulated subsequent to said step of encapsulating but prior to said step of severing.

12. The method of claim 5 wherein said leadframe is provided as a member of an array of leadframes and said members are singulated subsequent to said step of severing.

13. A package encasing at least one integrated circuit device comprising: a die pad, a plurality of leads, and at least a first ring circumscribing said die pad and disposed between said die pad and said plurality of leads, each of said die pad, plurality of leads and at least a first ring having first sides and opposing second sides;said at least one integrated circuit device bonded to said first side of said die pad and electrically interconnected to said first sides of said at least one ring and plurality of leads; anda molding resin encapsulating said at least one integrated circuit device and said first sides of said die pad, at least one ring and plurality of leads while said opposing second sides of said die pad, at least one ring and plurality of leads are not encapsulated in said molding resin.

14. The package of claim 13 wherein said opposing second sides form a common surface with a sidewall of said package.

15. The package of claim 14 wherein said opposing second sides are coated with a different metal.

16. The package of claim 13 wherein a second ring is disposed between said first ring and said plurality of leads.

17. The package of claim 16 wherein said opposing second sides form a common surface with a sidewall of said package.

18. The package of claim 17 wherein said opposing second sides are coated with a different metal.

19. The package of claim 17 wherein at least one of said first ring and said second ring has a desired voltage potential.

20. The package of claim 17 wherein at least one of said first ring and said second ring is electrically grounded.