The present invention relates to a method for manufacturing a semiconductor device.
A high speed operation of semiconductor devices such as semiconductor integrated circuit devices has recently been progressed. The high speed of operation has been realized by, for example, lowering the resistance of a wiring material. For that reason, instead of aluminum that has been used conventionally, copper having a low resistance than aluminum has been used for the wiring materials.
However, it is difficult to apply the existing dry etching technologies to process copper. This is because that the compound of copper formed while copper is being etched generally has a relatively lower vapor pressure to be evaporated. For example, technologies such as an Ar sputtering and a Cl gas RIE have been attempted, but these technologies were not able to be put to practical use due to the problem such as, for example, the attachment of copper to an inner wall of a chamber. For that reason, copper-based wiring is formed only using a damascene technology. The damascene technology is a technology that forms a trench along a wiring pattern in advance in an interlayer dielectric film, forms a thin copper film to fill the trench, and chemically and mechanically polishes the thin copper film using a CMP method, thereby remaining the copper only inside the trench.
However, in the damascene technology, the trench is formed in an interlayer dielectric film. For this reason, process that increases the relative dielectric constant of the interlayer dielectric film, such as forming of a trench, ashing a mask material used in the forming of the trench, and cleaning after the ashing, have to be involved.
An anisotropic dry etching method for copper, which does not depend on the damascene technology, is disclosed in Patent Document 1. The technology in Patent Document 1 forms a mask on a copper film, performs an anisotropic oxidation processing to the copper film through the mask, and etches the copper oxide by an organic acid gas.
However, copper is easily diffused into the interlayer dielectric film. For that reason, a Cu barrier film that suppresses the diffusion of the copper has to be formed prior to forming the copper film. In the damascene technology, the Cu barrier film may be simply and practically formed by forming the Cu barrier film and the copper film in this order after forming the trench in the interlayer dielectric film. However, in a case of the anisotropically etched copper film, a practical method of forming the Cu barrier film does not exist as of now as Patent Document 1 does not disclose how to form the Cu barrier film.
Meanwhile, a method called dual damascene technology is known as a type of damascene technology. The dual damascene technology concurrently forms on a single copper film a wiring pattern and a via pattern that electrically connects an upper layer wiring with a lower layer wiring. For that reason, an anisotropic etching also requires the technology that concurrently forms a wiring pattern and a via pattern.
However, the method for concurrently forming the wiring pattern and the via pattern on a single copper film using the anisotropic etching does not exist as of now as Patent Document 1 does not disclose the method.
Patent Document 1: Japanese Patent Laid-Open Publication No. 2010-27788.
An object of the present invention is to provide a semiconductor device manufacturing method capable of practically forming a Cu barrier film on an anisotropically etched copper film.
Another object of the present invention is to provide a semiconductor device manufacturing method capable of concurrently forming a wiring pattern and a via pattern on a single copper film using an anisotropic etching.
According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method including: forming a copper film on a Cu barrier film; forming a mask material on the copper film; anisotropically etching the copper film using the mask material as a mask until the Cu barrier film is exposed; and forming a plating film including a material that suppresses the diffusion of the copper on the anistropically etched copper film using an electroless plating method that uses a selective precipitation phenomenon which has a catalytic action for the copper film and does not have the catalytic action for the Cu barrier film, after removing the mask material.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method including: forming a copper film on a Cu barrier film; forming mask materials to be spaced apart from each other on the copper film; anisotropically etching the copper film the mask materials as a mask until the Cu barrier film is exposed; and forming an interlayer dielectric film having a space between the anisotropically etched copper films by depositing an insulating material on the anisotropically etched copper film to be pinched-off on the top of the copper film after removing the mask materials.
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method including: (1) forming a copper film on a barrier film; (2) forming a first mask material on the copper film; (3) anisotropically etching the copper film using the first mask material as a mask until the barrier film is exposed; (4) forming a second mask material on the anisotropically etched copper film after removing the first mask material; (5) anisotropically etching the copper film up to the midway of the copper film using the second mask material as a mask; and (6) forming an interlayer dielectric film around the anisotropically etched copper film by depositing an insulating material on the anisotropically etched copper film after removing the second mask material.
Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Further, common parts are referred to as common reference numerals in each of the exemplary embodiments.
(First Example)
As illustrated in
Next, as illustrated in
Next, mask materials 102 are removed as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
According to the first example of the first exemplary embodiment, the plating film that includes a material that suppresses the diffusion of the copper is formed in a single process on anisotropically etched copper film 101. The process uses the electroless plating method that uses the selective precipitation phenomenon which has the catalytic action for copper film 101 and does not have the catalytic action for Cu barrier film 100. In the present example, an alloy formed by making cobalt contain at least tungsten, for example, CoW film 104 is formed as the plating film in a single process. As described above, the alloy formed by making cobalt contain at least tungsten may be used for a Cu barrier film that suppresses the diffusion of copper.
Therefore, according to the first example of the first exemplary embodiment, an advantage may be obtained in that the Cu barrier film may be formed simply and practically on anisotropically etched copper film 101.
Also, according to the first example of the first exemplary embodiment, there is no process that increases the relative dielectric constant of interlayer dielectric film 105, such as, for example, forming a trench along a pattern of the inner wiring for interlayer dielectric film 105, ashing the mask material used for forming the trench, and cleaning after the ashing, which have been required in the damascene method. For that reason, a damaged layer does not occur in a portion of interlayer dielectric film 105 to be in contact with a side surface of copper film 101. Since the damaged layer does not occur in interlayer dielectric film 105, an advantage may be obtained in that the increase of the relative dielectric constant of interlayer dielectric film 105 is suppressed during the process, and the increase of wiring delay is suppressed, thereby attributing the high speed operation of semiconductor integrated circuit devices.
In addition, copper film 101 is metalized on substantially flat Cu barrier film 100. For that reason, in the first example of the first exemplary embodiment, it is not required to metalize copper film 101 in a fine trench as in the damascene method, and therefore an advantage may also be obtained in that it is more advantageous in further miniaturizing semiconductor integrated circuit devices.
Further, according to the first example of the first exemplary embodiment, a plating film that selectively suppresses the diffusion of the copper, for example, the CoW film, is formed on the surface of anisotropically etched copper film 101. For that reason, the Cu barrier film may not be formed in the trench. Because of the above reason, it is advantageous in further miniaturizing semiconductor integrated circuit devices.
(Second Example)
The second example of the first exemplary embodiment relates to a semiconductor device manufacturing method which may form an air gap structure using a less number of processes. Such an air gap structure is being developed, aiming to a semiconductor integrated circuit device having a higher operational speed.
First, as illustrated in
Next, as illustrated in
Basically, the CVD method is a conformal film forming method, but the film forming rate is higher at an entrance of a trench as compared to the bottom of the trench. For that reason, in a trench having high aspect ratio, insulating materials are pinched off, thereby being connected with each other at the entrance. As described above, on anisotropically etched copper film 101, the insulating materials may be deposited to be pinched-off on the top of copper film 101, thereby forming a space 107 within interlayer dielectric film 106. That is, an air gap may be formed. The relative dielectric constant within space 107 is 1. For this reason, an effective dielectric constant may be further lowered between copper films 101.
Next, as illustrated in
According to the second example of the first exemplary embodiment as described above, the number of the processes in forming the air gap structure may be reduced.
Specifically, for example, when a damascene method is used, an air gap structure cannot be obtained unless the following processes (1) to (5) are performed.
(1) Forming a thin film.
(2) Forming a trench in the thin film.
(3) Burying copper in the trench.
(4) Peeling the thin film.
(5) Forming an interlayer dielectric film using a CVD method.
Whereas, according to the second example of the first exemplary embodiment, since copper film 101 is directly patterned, the above processes (1) to (4) may be omitted.
That is, according to the second example of the first exemplary embodiment, the advantages as in the first example may be obtained. Further, interlayer dielectric film 106 with space 107 may be formed through the reduced number of processes by depositing the insulating material on anisotropically etched copper film 101 such that the insulating material is pinched-off on the top of copper film 101.
Accordingly, the effective dielectric constant between anisotropically etched copper films 101 may be lowered without increasing the number of processes, and thus, an advantage may be obtained in that the manufacturing time in manufacturing semiconductor integrated circuit devices may be shortened.
(First Example)
First, as illustrated in
Next, as illustrated in
Next, first mask materials 202 are removed as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, second mask material 204 is removed as illustrated in
Next, as illustrated in
Next, as illustrated in
Basically, the CVD method is a conformal film forming method, but the film forming rate is higher at an entrance of a trench as compared to the bottom of the trench. For that reason, in a trench having a high aspect ratio, the insulating materials are pinched off at the entrance, thereby being connected with each other at the entrance. As described above, on anisotropically etched copper film 201, the insulating materials may be deposited to be pinched-off on the top of copper film 201, thereby forming a space 207 within interlayer dielectric film 206. That is, an air gap may be formed. The relative dielectric constant within space 207 is 1. For this reason, an effective dielectric constant may be further lowered between copper films 201.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Second layered copper film 210 may also be formed to a second layered inner wiring pattern and a via pattern by repeating the manufacturing method described above with reference to
According to the first example of the second exemplary embodiment, since a inner wiring pattern and a via pattern are formed in a single copper film 201, there is no process that increases the relative dielectric constant of interlayer dielectric film 206, such as, for example, forming a trench along the inner wiring pattern and the via pattern for interlayer dielectric film 206, ashing the mask material used for the forming of the recess, and cleaning after the ashing, which have been required in the damascene method. For that reason, a damaged layer does not occur in a portion of interlayer dielectric film 206 to be in contact with a side surface of copper film 201. Since the damaged layer does not occur in interlayer dielectric film 206, the increase of the relative dielectric constant of interlayer dielectric film 206 may be suppressed during the processes, and the increase of the wiring delay may be prevented to attribute the high speed operation of the semiconductor integrated circuit devices.
Further, first layered copper film 201 is metalized on substantially flat barrier film 200, and second layered copper film 209 is metalized on substantially flat barrier film 200. For that reason, in the first example of the second exemplary embodiment, it is not required to metalize first layered copper film 101 and second layered copper film 109 in a fine trench as in the damascene method, and therefore, the first example is more advantageous in further miniaturizing semiconductor integrated circuit devices.
(Second Example)
In the first example of the second exemplary embodiment, descriptions were made for an example where the primer of first layered copper film 201 is first layered barrier film 200.
The present second example is an example where the primer of the first layered film 201 is a silicon oxide film.
As illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Then, a semiconductor integrated circuit device is manufactured according to the manufacturing method described with reference to
As in the present example, when barrier film 212 has conductivity, first layered copper films 201 may be suppressed from being shorted with each other, by patterning first layered copper film 201 along with barrier film 212.
(Third Example)
In the first example of the second exemplary embodiment, a SiCN film was used as barrier film 208 for second layered copper film 209.
In the present third example, the surface of interlayer dielectric film 206 is directly converted into a barrier layer.
As illustrated in
Next, as illustrated in
According to the third example of the second exemplary embodiment, since the surface of interlayer dielectric film 206 is directly converted into a barrier layer, a process that forms vias in barrier film 208 may be omitted as compared with the first example of the second exemplary embodiment. For that reason, an advantage may be obtained in that the number of the manufacturing processes may be reduced in manufacturing semiconductor integrated circuit devices, thereby shortening the manufacturing time.
[Modified Example]
Although the present invention has been described above according to the exemplary embodiments, the present invention is not limited to the exemplary embodiments, and various modifications thereof may be made.
For example, the method of anisotropically etching a copper film may include three methods as described below.
A method in which a mask material is used as a mask, oxygen ions are irradiated to a copper film under an organic acid gas atmosphere, the copper film is anisotropically dry-etched until Cu barrier film is exposed or up to the midway of the copper film.)
A method in which a copper film is anisotropically etched up to a Cu barrier film or up to midway of the copper film using a mask material as a mask to form a copper oxide, and the formed copper oxide is dry-etched or wet-etched.
A method in which a process to anisotropically oxidize a surface of a copper film using a mask material as a mask and a process to dry-etch the a copper oxide formed on the surface using an organic acid gas are repeated until a Cu barrier film is exposed or up to the midway of the copper film.
An example of the organic acid gas used in the dry-etching by the organic acid gas may include a carboxylic acid containing carboxylic-group (—COOH).
As the carboxylic acid, a carboxylic acid which is expressed by formula (1) as follows may be exemplified:
R3—COOH (1)
(R3 may be selected from hydrogen, or a straight chain or branched chain type alkenyl group or alkyl group of C1 to C20)
Also, in the method (□), an wet-etching by a solution containing an organic acid or a solution containing a hydrofluoric acid may be used for the etching of the copper oxide, in addition to the dry-etching by organic acid gas.
A solution used for the wet-etching by the solution containing an organic acid may include a solution containing at least one selected from the group consisting of:
a citric acid having a carboxylic group,
an ascorbic acid having a carboxylic group,
a malonic acid having a carboxylic group, and
a malic acid having a carboxylic group.
Meanwhile, the methods (□) and (□) have an advantage in that the throughput is good and copper film 101 may be anisotropically etched, as compared with the method (□). This is because although in the method (□), a semiconductor wafer is continuously transferred between an oxidation apparatus and a dry-etching apparatus until Cu barrier film 100 is exposed, the method (□) may anisotropically etch a copper film within a single chamber and the method (□) may anisotropically etch a copper film within a single chamber and then, transfer the semiconductor wafer to another chamber to etch the copper oxide.
Accordingly, the methods (□) and (□) have a good throughput, and may anisotropically etch copper film 101 until Cu barrier film 100 is exposed, as compared with the method (□).
Number | Date | Country | Kind |
---|---|---|---|
2010-193985 | Aug 2010 | JP | national |
2010-193986 | Aug 2010 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/JP2011/067400 | 7/29/2011 | WO | 00 | 3/27/2013 |