This invention relates generally to methods for packaging (i.e., encapsulating) semiconductors and more particularly to methods for packaging semiconductors at a wafer level (i.e., wafer-level packaging).
As is known in the art, traditionally in the microelectronics industry, electrical devices are fabricated on wafers and then diced into individual chips. The bare chips would then get assembled with other components into a package for environmental and mechanical protection. In commercial applications, the chips were generally assembled into plastic packages. In military applications, where electronics are generally exposed to harsher environments, the parts are generally housed in a hermetic module. Such packages or modules would then be further assembled unto circuit boards and systems. However, as electronic systems advance, there is a need to increase functionality while decreasing the size and cost of components and sub-systems.
One way to reduce size and cost is to create packages at the wafer level and then subsequently dicing the wafer into individual packaged semiconductors (i.e., wafer-level packaging). Many methods have been suggested to create wafer-level packages. One method, call wafer bonding, is to bond a wafer with pre-formed cavities over the device wafer. The bonding can be achieved through thermal bonding, adhesive or solder bonding, see for example, Rainer Pelzer, Herwig Kirchberger, Paul Kettner, “Wafer-to Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications”, 6th IEEE International Conference on Electronic Packaging Technology 2005 and A. Jourdain, P. De Moor, S. Pamidighantam, H. A. C. Tilmans, “Investigation of the Hermeticity of BCB-Sealed Cavities For Housing RF-MEMS Devices”, IEEE Electronic Article, 2002
However, this method introduces a lot of complexity and issues into the process. Thermal bonding is generally achieved at very high temperatures, in excess of 400 C. Adhesive bonding can be achieved at lower temperature, but adhesive outgassing is a concern. Therefore wafer bonding is not a suitable and cost-effective method for some applications.
Another approach is to use Liquid crystal polymer (LCP). It has recently become a popular candidate for various packaging approaches, due to its excellent electrical, mechanical and environmental properties. The material comes in rolls and can be laminated unto the wafer as a film. A general method is to use multiple stacks of LCP. Individual holes were created in a layer of LCP and laminated over the wafer so that the device or FETs are exposed through the holes. This first layer of LCP forms the sidewall of the cavity. Then a second layer of LCP is laminated over the entire wafer, thus enclosing the cavity, see Dane. C. Thompson, Manos M. Tentzeris, John Papapolymerou, “Packaging of MMICs in Multilayer of LCP Substrates,” IEEE Microwave and Wireless Components Letters, vol. 16, No. 7, July 2006. Single stack of LCP can also be used, but cavities still must be formed on the material before lamination unto wafer, see Dane. C. Thompson, Nickolas Kinglsley, Guoan Wang, John Papapolymerou, Manos M. Tentzeris, “RF Characteristics of Thin Film Liquid Crystal Polymer (LCP) Packages for RF MEMS and MMIC Integration”, Microwave Symposium Digest, 2005 IEEE MTT-S International, 12-17 Jun. 2005 Page(s):4 pp. and Mogan Jikang Chen, Anh-Vu H. Pham, Nicole Andrea Evers, Chris Kapusta, Joseph Jannotti, William Kornrumpf, John J. Maciel, Nafiz Karabudak, “Design and Development of a Package Using LCP for RF/Microwave MEMS Switches”, IEEE Transactions on Microwave Theory and Techniques, vol. 54, No. 11, November 2006. The prior work mentioned above involve forming a pattern on the cavity material first and then bonded to the device wafer. There are several disadvantages: First, this is a complicated and cumbersome process. One must ensure very accurate alignment in pattern formation and wafer bond; second, the cavities are generally large that covers the entire chip due to the alignment difficulty. There is not much flexibility in creating cavities that covers just the active devices and individual passive components. Generally, with a larger cavity, not only that the risk for mechanical failure is greater, environmental protection of the package is also compromised, see Aaron Dermarderosian, “Behavior of Moisture in Sealed Electronic Enclosures,” International IMAPS conference in San Diego, October of 2006. These issues with traditional methods limit the manufacturability and performance of the package.
Besides reducing size and cost, a wafer-level package also needs to offer the same level of environmental protection as the traditional packages. They are generally required to pass the leak detection test under Method 1014, MIL-STD-883 and the humidity testing under JEDEC Standard No. 22-A101-B. One way to protect the devices is through the application of hermetic coatings, see M. D. Groner, S. M. George, R. S. McLean and P. F. Carcia, “Gas diffusion barriers on polymers using A12O3 atomic layer deposition,” Applied Physics Letters, 88, 051907 (2006), but direct application of the coating unto certain semiconductor devices can degrade performance.
Another way is to make the package itself hermetic. Wafer bonding methods that fuse silicon or glass together generally can achieve hermetic performance. Plastic packages such as LCP and BCB while capable of passing initial hermeticity tests as defined by MIL-Std 883 Method 1014, are described as near-hermetic due to the diffusion rates through these materials compared to glass and metals, see A. Jourdain, P. De Moor, S. Pamidighantam, H. A. C. Tilmans, “Investigation of the Hermeticity of BCB-Sealed Cavities For Housing RF-MEMS Devices”, IEEE Electronic Article, 2002 and Dane. C. Thompson, Nickolas Kinglsley, Guoan Wang, John Papapolymerou, Manos M. Tentzeris, “RF Characteristics of Thin Film Liquid Crystal Polymer (LCP) Packages for RF MEMS and MMIC Integration”, Microwave Symposium Digest, 2005 IEEE MTT-S International, 12-17 Jun. 2005 Page(s):4 pp
In multichip-module packaging approaches, the chips are packaged by spinning or laminating the dielectric film over the entire chip. Prior work have been done using various combination of Kapton E, BCB, SPIE, etc., seeVikram B. Krishnamurthy, H. S. Cole, T. Sitnik-Nieters, “Use of BCB in High Frequency MCM Interconnects”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 19, No. 1, February 1996. Although this reduces the processing complexity but performance is degraded because there is no air cavity over the active devices. A dielectric film deposited directly on top of transistors generally degrades its performance due to the increased parasitic capacitance. The multichip-module packaging is a chip-level rather than a wafer-level approach.
In another wafer-level packaging approach, caps made from different material, such as LCP, glass, etc. were dropped unto the wafer to cover individual chips. The caps were sealed in place using adhesives. Again, this is a complex process that picks and places the caps on individual chips; see George Riley, “Wafer Level Hermetic Cavity Packaging”, http://www.flipchips.com/tutorial43.html
In accordance with the present invention, a method is provided for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion device-exposing openings to expose the devices and electrical contacts pads openings; mounting a rigid dielectric layer over the formed material, such rigid material being suspended over the device exposing openings (i.e., cavities) in the material and over the electrical contacts pads openings in the material.
In one embodiment, the method includes forming electrical contact pad openings in portions of the rigid dielectric layer disposed over electrical contact pads of the devices with other portions of the rigid dielectric layer remaining suspended over the device exposing openings in the material.
In another embodiment, the environmental protection capability of the package can be enhanced by depositing environmentally robust coatings after the application of the rigid material. Thus, the devices can achieve hermetic-like performance but without the cost and complexity of traditional hermetic packages. In addition, performance degradation of the device can be avoided because the coating does not directly coat the device.
Thus, rather than form a pattern on the cavity material first and then bond to the device wafer, a complex and time consuming process having alignment as an issue and where the size of the cavity is generally the size of the entire chip, in accordance with the invention by using a photo-patternable, etchable material cavities are formed unto the wafer using conventional photolithographic techniques. Thus, with such method, a simple and cost-effective way is provided to make wafer-level packages that is environmentally robust and yet maintains optimal circuit performance.
In one embodiment, an additional layer or layers of photoprocessable material and photosensitive epoxy resists (such as Benzocyclobutene (BCB) and SU—8) is formed on either the wafer, the rigid dielectric or both to aid in cavity formation and bonding of the rigid dielectric layer to the lithographically formed on-wafer coating. These coatings may be full or partial cured to aid adhesion at lower lamination pressure and temperature than otherwise required. This protects the semiconductor devices from any potential damage due to high temperature processing and aids in controlling ground/signal spacing, and/or compensates for wafer to dielectric height non-uniformities.
In accordance with another feature of the invention, a package for a semiconductor device formed in a surface portion of a semiconductor wafer is provided. The package includes a lithographically processable, etchable material disposed on the surface portion of the semiconductor wafer having openings therein to expose the device and electrical contacts pads openings therein to expose an electrical contact pad for device and a rigid dielectric layer over the lithographically processable, etchable material, such rigid material being suspended over the device exposing opening in the material.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
Referring now to
Next, a lithographically processable, etchable material 30 is deposited over the upper surface portion of the semiconductor wafer 10, as shown in
The BCB material 30 can be dispensed as a liquid, spun on, exposed, developed and cured, all using conventional semiconductor fabrication equipment. Because BCB can be patterned by conventional photolithographic technique, it can achieve alignment tolerances and critical dimensions similar to that of photoresist (limited by film thickness). A spin-on process is preferable to a lamination process (such as that for LCP) from a mechanical and process simplicity standpoint. The spin-on process introduces less stress to the wafer, especially for the mechanical fragile structures such as air bridges and is more capable of self leveling over complex circuit topologies.
Next, the material 30 is photolithographically processed, as shown in
After patterns are formed on the BCB material 30, the openings or cavities 32 are enclosed using a mechanically strong, i.e., rigid self-supporting layer 40 that has good adhesion to BCB material 30. One material for layer 40 is LCP, which can be laminated over the BCB material 30, as shown in
If LCP adhesion to BCB is difficult to achieve at a safe processing temperature for the semiconductor device, a thin layer of BCB material 31 as shown in
To make electrical connections to the circuit devices 12, laser ablation can be used to remove portions 54 (
Here, the bond pads 16, 18 can be left exposed for wire bonding as shown in
Next, the metal 80 may be patterned for additional contacts or structures, as showing in
A number of embodiments of the invention have been described. For example, materials other than BCB may be used such as SU—8. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.