Method of interconnecting electronic components using a plurality of conductive studs

Abstract
A method of interconnecting electronic components by using a plurality of conductive studs on a surface of a first electronic component and a plurality of corresponding conductive vias on the surface of a second electronic component. Camber on the surface of electronic components may be overcome by coating the surface with a dielectric, planarizing the dielectric, and forming conductive vias corresponding to the contact pads thereon. The conductive studs are substantially lead-free and preferably comprise of copper.
Description




CROSS-REFERENCE TO RELATED APPLICATIONS




Aspects of the present invention are related to subject matter disclosed in co-pending applications entitled “Z-Axis Compressible Polymer With Fine Metal Matrix Suspension,” Attorney Docket No. FI9-98-165, filed on even date herewith and assigned to the assignee of the present invention, the subject matter of which is hereby incorporated by reference.




BACKGROUND OF THE INVENTION




1. Field of the Invention




This invention relates to electronic components which utilize a substantially lead-free interconnect process when forming an electronic module.




2. Description of Related Art




As the circuit density increases on integrated circuit devices such as silicon microprocessors, there is a need for high density interconnection between such a device and a chip carrier to which these devices are typically attached. Traditional methods of joining using solder ball arrays may become difficult with such dense circuitry.




Typically, solder ball arrays require fluxes when joining lead based solders. With connection densities reaching about 150 μm or below, it becomes difficult to clean such fluxes. Without effective flux cleaning, underfill materials which are used to enhance reliability of the resulting electronic module run the risk of delaminating. The use of lead based solder also increases the difficulties in disposing of any waste.




The circuit density also poses problems with shorting between adjacent solder balls particularly on chip carriers having camber or deformities. Typical chip carriers such as a ceramic substrate exhibit about 25 to about 50μm camber as measured from a flat surface of the substrate. When a device with solder balls is joined to such a carrier, some of the solder balls contact the mating pads. Due to the wetting action of the solder the device is pulled down and remaining solder balls which make contact further pull down the chip. As a result, after joining, many of the solder balls are in closer proximity to each other and may be contacting each other leading to shorts.




Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of interconnecting high circuit density electronic components utilizing substantially lead-free interconnects which do not require flux and takes into account the deformities on a substrate surface.




It is another object of the present invention to provide an electronic module having high circuit density electronic components which utilizes substantially lead-free interconnects which do not require flux and takes into account the deformities on a substrate surface.




Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.




SUMMARY OF THE INVENTION




The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of interconnecting electronic components comprising the steps of: (a) providing a first electronic component having electrical devices with corresponding bonding pads, the first electronic component having a patterned dielectric film formed thereon, the dielectric film having a plurality of protruding conductive studs, the studs corresponding to the bonding pads and adapted for electrical connection to the electrical devices; (b) providing a second electronic component having a dielectric film formed thereon, the dielectric film adapted to offset camber on a surface of the second electronic component having a plurality of conductive vias corresponding to the studs on the first electronic component; (c) providing an interposer having electrical interconnections corresponding to the studs and vias; and (d) aligning and contacting the first electronic component and the second electronic component with the interposer disposed therebetween, such that the studs of the first electronic component and the vias of the second electronic component are adapted to be electrically and mechanically interconnected by the interposer.




Preferably, step (a) comprises providing a semiconductor chip having electrical devices with corresponding bonding pads, the chip having a patterned and cured polyimide film formed thereon, the polyimide film having a plurality of protruding conductive metal studs, the studs corresponding to the bonding pads and adapted for electrical connection to the electrical devices.




Preferably, in step (a) the studs protruding about 15 μm to about 20 μm from a surface of the dielectric film and having a diameter of about 50 μm to about 75 μm and may comprise copper.




Preferably, step (b) comprises providing a substrate having a cured polyimide film formed thereon, the polyimide film having a plurality of copper vias substantially planar to a surface of the film and capped with gold, the vias corresponding to the studs on the first electronic component. Preferably, in step (b) the vias have a height of at least about 15 to about 30 μm and may protrude about 10 to about 15 μm from a surface of the dielectric film.




Preferably, step (b) comprises providing a substrate having a dielectric film formed thereon, the dielectric film adapted to offset camber on a surface of the substrate having a plurality of protruding conductive metal vias corresponding to the studs on the first electronic component.




Preferably, step (c) comprises providing a flexible interposer having electrical interconnections comprising conductive metal vias with palladium dendrites formed on a top exposed surface and a bottom exposed surface.




The present invention is directed to, in another aspect, an electronic module comprising a first electronic component having electrical devices with corresponding bonding pads, the first electronic component having a first dielectric film formed thereon, the film having a plurality of conductive studs corresponding to the bonding pads and adapted for electrical connection to the electrical devices; a second electronic component having a second dielectric film formed thereon, the film having a plurality of conductive vias corresponding to the studs on the first electronic component; an interposer disposed between the first and second electronic components having a plurality of interconnections corresponding to the studs of the first electronic component and the vias of the second electronic components. Preferably, the plurality of conductive studs protrude about 15 to about 20 μm from a surface of the first dielectric film with a diameter of about 50 to about 75 μm.











BRIEF DESCRIPTION OF THE DRAWINGS




The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:





FIG. 1

is a cross-sectional view of a silicon wafer having the substantially lead-free protruding conductive studs of the present invention.





FIG. 2

is a cross-sectional view of a singulated chip or die made in accordance with a method of the present invention.





FIG. 3

is a cross-sectional view of a deformed chip carrier planarized in accordance with a method of the present invention.





FIG. 4

is a cross-sectional view of a chip, a chip carrier and an interposer when practicing a method of the present invention.





FIG. 5

is a cross-sectional view of an interposer utilized in the present invention.











DESCRIPTION OF THE PREFERRED EMBODIMENT(S)




In describing the preferred embodiment of the present invention, reference will be made herein to

FIGS. 1-5

of the drawings in which like numerals refer to like features of the invention. Features of the invention are not necessarily shown to scale in the drawings.




The present invention discloses a novel interconnect methodology using a substantially lead-free stud that provides an essentially planar surface for chip to substrate interconnection. The present invention reduces the difficulties encountered when joining a chip to a substrate having deformities on the substrate surface which cause the traditional solder interconnects to flow away from a solder pad that it is not in contact with. Additionally, the use of an interconnect technology which does not utilize lead based solder is of significant environmental benefit. In preparing a chip and substrate for interconnection in accordance with the present invention, an array of protruding lead-free metal studs are formed on the silicon device as shown in

FIG. 1. A

silicon wafer


10


is provided with, preferably, a number of electrical devices formed thereon encompassed in wiring layer


20


. After the last wiring level is finished on wafer


10


, a blanket layer of a dielectric material


30


is preferably applied to the surface of wafer


10


.




Dielectric material


30


is preferably a photosensitive material, most preferably polyimide, and is adapted to have a thickness of approximately 40 to 50 μm after full curing. Depending upon the dielectric chosen, the curing conditions would be known to one of ordinary skill in the art. Dielectric


30


is patterned with a standard photo expose, develop and cure process. The pattern exposed on the dielectric would correspond to bonding pads electrically connected to the electrical devices formed on wafer


10


.




A blanket layer of a conductive material, preferably a metal, is deposited over wafer


10


to fill the pattern of holes in dielectric


30


. Where the conductive material is a metal, to enhance adhesion of the metal, a first metal may be preferably sputter deposited into the pattern holes of dielectric


30


, followed by the sputter deposition of a second metal which has better conductivity. Preferably, the metal is chromium/copper such that chromium may be sputter deposited first to provide better adhesion of the copper. Upon substantially filling the pattern holes of dielectric


30


, planarization techniques are used to planarize the studs


40


with the dielectric


30


. Typical planarization techniques may be chemical mechanical polishing.




At this stage, it is preferred to plasma etch the dielectric


30


such that studs


40


protrude about 15 μm to about 20 μm from a surface of the dielectric


30


. The plasma etching may be carried out in an oxygen atmosphere under conditions which allow for controllable etching of the dielectric


30


. Most preferably, the studs


40


have a diameter of about 50 μm to about 70 μm. Studs


40


, now exposed and protruding from a surface of dielectric


30


, may be coated with about 500 to about 1000 Å of gold, preferably by electroless plating. The wafer is then subjected to a diffusion step preferably in an inert atmosphere at about 200 to about 300° C. Wafer


10


is then singulated to produce the individual chip or die


12


as shown in

FIG. 2

for connection to a chip carrier.





FIG. 3

shows a typical chip carrier


15


having a slight deformity as shown by camber C. Typical chip carriers such as a ceramic substrate typically exhibit about 25 μm to about 50 μm of camber. Chip carrier


15


is planarized by utilizing a process where a dielectric layer


50


is applied and cured on chip carrier


15


such that a thickness of camber and dielectric


50


of about 60 to about 90 μm, preferably about 75 μm, is achieved. Preferably, dielectric


50


comprises polyimide.




Dielectric


50


is planarized using chemical mechanical polishing or other techniques to produce a flat surface with a maximum thickness on the camber of about 40 μm. An array of vias


60


are created preferably by laser ablation which correspond to the studs


40


for interconnection to the corresponding electrical devices on wafer


10


. Preferably, the vias


60


are substantially filled with a conductive material such as a metal. Where vias


60


comprise metal, to enhance adhesion a blanket layer of a first metal is sputter deposited followed by sputter deposition of a second more conductive metal.




Dielectric


50


is again planarized to create a level array of vias


60


. If desired, the exposed conductive surfaces may be capped with gold plating and followed by diffusion. In another embodiment shown in

FIG. 3A

, vias


60


A may protrude about 10 μm to about 15 μm from the surface of dielectric


50


by etching back a portion of dielectric


50


. Preferably, vias


60


comprise chromium/copper having a minimum height on chip carrier


15


of between about 15 μm to about 30 μm where the chip carrier has little deformity and a maximum via height of about 30 μm to about 60 μm where chip carrier


15


has a high degree of deformity, or camber.





FIG. 4

illustrates a method of interconnecting a chip to a substrate in accordance with a method of the present invention. Chip


12


is shown as being aligned over chip carrier


15


such that protruding studs


40


A correspond to vias


60


. An interposer


100


is aligned and disposed between chip


12


and chip carrier


15


. To connect the array of studs


40


A with vias


60


, heat and pressure are usually applied after interposer


100


, chip


12


and chip carrier


15


are contacted together. A preferred interposer is disclosed in the aforementioned co-pending application entitled “Z-Axis Compressible Polymer With Fine Metal Matrix Suspension,” Attorney Docket No. FI9-98-165 filed on even date herewith and assigned to the assignee of the present invention, although other interposers may also be contemplated.




Preferably, interposer


100


comprises polyimide or some other suitable flexible material and has through-studs


150


which correspond to studs


40


A and vias


60


for interconnecting chip carrier


15


to chip


12


. Most preferably, through-studs


150


on interposer


100


have palladium dendrites


155


plated on both exposed surfaces. The dendrites


155


make contact with the matching array of studs


40


A and vias


60


. The protrusion of studs


40


A assures that contact is first made between the matching array of studs


40


A when pressure is applied to interposer


100


. This allows for small variations in the interposer thickness and tolerances in the planarity achieved in the leveled camber of chip carrier


15


. Interposer


100


, not being permanently bonded to chip


12


or chip carrier


15


, may be used during test and burn-in of the chip


12


since they are easily separable.




Once chip


12


and chip carrier


15


have passed inspection and require permanent bonding, interposer


100


may be replaced with an interposer made from a thin epoxy material about 20 μm to about 40 μm thick with the suitable array of through-studs filled with a conductive material such as gold or silver. The epoxy interposer is then aligned to both chip


12


and chip carrier


15


and permanently bonded by applying heat and pressure. Vias


60


on chip carrier


15


and the protruding studs


40


A on chip


12


assure that good electrical contacts are made. Of course, other methods of permanently bonding chip


12


and chip carrier


15


may also be contemplated.




The present invention achieves the objects recited above. The present invention discloses a novel interconnect methodology using a substantially lead-free stud that provides an essentially planar surface for chip to substrate interconnection. The use of the protruding studs provides a substantially planar surface for interconnection with a chip carrier or substrate. Additionally, camber on the surface of the substrate may be overcome by coating the substrate with a dielectric film and planarizing the dielectric film to provide a substantially planar surface for interconnection.




While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.




Thus, having described the invention, what is claimed is:



Claims
  • 1. An electronic module comprising:a first electronic component having electrical devices with corresponding bonding pads, said first electronic component having a first dielectric film formed thereon, said film having a plurality of protruding conductive studs corresponding to the bonding pads and adapted for electrical connection to the electrical devices; a second electronic component having a second dielectric film formed thereon, said film having a plurality of conductive vias corresponding to the studs on said first electronic component; an interposer disposed between said first and second electronic components having a plurality of interconnections corresponding to the studs of said first electronic component and the vias of said second electronic components to adapt for an electrical interconnection therebetween.
  • 2. The electronic module of claim 1 wherein said first dielectric film comprises polyimide.
  • 3. The electronic module of claim 1 wherein said plurality of conductive studs comprise copper studs.
  • 4. The electronic module of claim 1 wherein prior to forming said module, said plurality of conductive studs protrude about 15 to about 20 μm from a surface of said first dielectric film with a diameter of about 50 to about 75 μm.
  • 5. The electronic module of claim 1 wherein said second dielectric film offsets camber on a surface of said second electronic component.
  • 6. The electronic module of claim 5 wherein said second dielectric film offsets about 40 to about 50 μm of camber on a surface of said second electronic component.
  • 7. The electronic module of claim 1 wherein said plurality of conductive vias comprise copper vias.
  • 8. The electronic module of claim 1 wherein said interposer comprises an epoxy material about 20 to about 40 μm thick having a plurality of interconnections comprising a conductive material wherein upon heating and compressing said module, said first and second electronic components are substantially permanently bonded to said interposer.
  • 9. The electronic module of claim 8 wherein said plurality of interconnections of said interposer comprise gold or silver.
  • 10. The electronic module of claim 8 wherein said plurality of interconnections of said interposer further include a plurality of dendrites protruding from said interconnections.
  • 11. An electronic module comprisinga semiconductor chip having electrical devices with corresponding bonding pads, said semiconductor chip having a first dielectric film formed thereon, said film having a plurality of protruding conductive studs corresponding to the bonding pads and adapted for electrical connection to the electrical devices; a substrate having a cambered surface with a planarized second dielectric film formed thereon, said film having a plurality of conductive vias of varying depths corresponding to the studs on said first electronic component; an interposer disposed between said semiconductor chip and said substrate having a plurality of interconnections corresponding to the studs of said semiconductor chip and the vias of said substrate to adapt for an electrical interconnection therebetween.
  • 12. The electronic module of claim 11 wherein said studs comprise copper.
Parent Case Info

This is a divisional of copending application(s) Ser. No. 09/315,374 filed on May 18, 1999, now U.S. Pat. No. 6,258,625.

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