Method of making printed circuit board with varying depth conductive holes adapted for receiving pinned electrical components

Abstract

A method of making a printed circuit board in which openings of different length are formed using a cover atop one of the openings to prevent dielectric material from an interim layer of heat-deformable dielectric material from entering the opening when the sub-composite having the opening therein is bonded to a second sub-composite. The bonded sub-composites are then provided with a second opening which extends there-through, this second opening being longer than the first. Pins of an electrical component may then be inserted within the first and second openings of different length.

Description

TECHNICAL FIELD

This invention relates to printed circuit (or wiring) boards and particularly to multilayered printed circuit boards having a plurality of conductive holes therein. Even more particularly, the invention relates to such boards which are adapted for having one or more electrical connectors positioned thereon and electrically coupled thereto.

BACKGROUND OF THE INVENTION

As indicated from the following listing of patents, there are different methods of making multilayered printed circuit boards (hereinafter also referred to as PCBs) known today. In the manufacture of some printed circuit boards, for example, it has become commonplace to produce printed circuitry on both sides of a planar rigid or flexible insulating substrate. In addition, such boards also typically include several parallel and planar, alternating inner layers of insulating substrate material and conductive metal. The exposed outer sides of the laminated structure are typically provided with circuit patterns, and the metal inner layers typically contain circuit patterns, except in the case of internal power or ground planes which are usually substantially solid, albeit also containing clearance openings or other openings if desired.

In multilayered printed circuit boards such as these, it is necessary to provide conductive interconnections between the various conductive layers or sides of the board. This is commonly achieved by providing metallized conductive holes in the board which communicate with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made with almost if not all of the conductive layers. In such a case, conductive holes are also typically provided through the entire thickness of the board. For these, as well as other applications, it is often desired to also provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, holes referred to as “blind vias”, passing only part way through the board, are provided. In still another case, such multilayered boards often require internal holes referred to simply as “vias” which are located entirely within the board's structure and covered by external layering, including both dielectric and conductive. Such internal “vias” are typically formed within a sub-part structure (sub-composite) of the final board and then combined with other layers (including other sub-composites) during final lamination of the board. For purposes of this application, the term “thru-hole” is meant to include conductive holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as an “internal via” which is internal “captured” by the board's outer layers.

To provide the desired circuit pattern on the board, the art has developed a variety of manufacturing sequences, many of which fall into the broad categories of “subtractive” or “additive” techniques. Common to subtractive processes is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Additive processes, on the other hand, begin with exposed substrate surfaces (or thin commoning metallization layers for additive electroplate) and build up thereon of metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., called photo-resist in the printed circuit board field).

Typically, thru-holes are drilled (including mechanically or more recently using lasers) or punched into or through the board at desired locations. Drilling or punching provides newly-exposed surfaces including via barrel surfaces and via peripheral entry surfaces. The dielectric substrate, comprising a top surface, a bottom surface, and at least one exposed via hole surface, consisting partly or entirely of insulating material, is then metallized, generally by utilization of electro-less metal depositing techniques, albeit other deposition processes are also known in the field.

In the manufacture of circuitized printed circuit boards, a dielectric sheet material is typically employed as the base component for the substrate. This base component is usually comprised of an organic material, such as fiberglass-reinforced epoxy resin (also referred to in the field as, simply, “FR4”), polytetrafluoroethylene (e.g., Teflon, a trademark of E.I. duPont deNemours & Company), Driclad dielectric material (Driclad being a trademark of Endicott Interconnect Technologies, Inc.), etc. Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate is typically “seeded” and plating then occurs. Such processing is known in the field and further description is not believed necessary, except to add that known metals used for plating the dielectric barrel to form the thru holes include copper, nickel and gold.

Examples of methods of making boards, including providing same with such thru holes, are shown and described in the following U.S. Letters Patents:

6,015,520 Method For Filling Holes in Printed Wiring Boards
6,073,344 Laser Segmentation of Plated Through-Hole Sidewalls
          To Form Multiple Conductors
6,188,027 Protection of a Plated Through Hole From Chemical
          Attack
6,281,446 Multi-Layered Circuit Board And Method of Manufacturing
          The Same
6,349,871 Process For Reworking Circuit Boards
6,493,861 Interconnected Series of Plated Through Hole Vias and
          Method of Fabrication Therefore
6,495,772 High Performance Dense Wire For Printed Circuit Board
6,518,516 Multilayered Laminate
6,626,196 Arrangement and Method For Degassing Small-High Aspect
          Ratio Drilled Holes Prior To Wet Chemical Processing
6,628,531 Multi-Layer and User-Configurable Micro-Printed
          Circuit Board
6,630,630 Multilayer Printed Wiring Board and Its Manufacturing
          Method
6,630,743 Copper Plated PTH Barrels and Methods For Fabricating
6,631,558 Blind Via Laser Drilling System
6,631,838 Method For Fabricating Printed Circuit Board
6,638,690 Method For Producing Multi-Layer Circuits
6,638,858 Hole Metal-Filling Method
6,809,269 Circuitized Substrate Assembly And Method Of Making
          Same
6,832,436 Conductive Substructures Of A Multilayered Laminate
6,872,894 Information Handling System Utilizing Circuitized
          Substrate

The present invention is able to produce a printed circuit board which is capable of having high speed signals pass through the signal conductors thereof, another highly desirable feature required of many of today's newer boards. By the term “high speed” is of course also meant to mean high frequency. Further description is provided below.

The present invention represents a new and unique method of forming conductive thru holes in a printed circuit board in comparison to those above and other processes known in the art. It is believed that such a method, and the board resulting there-from, will represent a significant advancement in the art.

DESCRIPTION OF THE INVENTION

It is, therefore, a primary object of the present invention to enhance the printed circuit board art by providing a new and unique method of producing such boards.

It is another object of the invention to provide such a process and resulting board in which several conductive thru holes are formed to interconnect various conductive layers of the board in a new and expeditious manner.

It is still another object of the invention to provide such a process which can be implemented using conventional printed circuit board technologies and thus performed with little or no increased cost over conventional techniques.

According to one aspect of the invention, there is provided a method of making a multilayered printed circuit board (PCB), the method comprising providing a first sub-composite including at least one dielectric layer and at least one opening therein having first and second opposing open end portions and extending substantially through the at least one dielectric layer, positioning a cover on the first opposing open end portion of the at least one opening, aligning the first sub-composite having the at least one opening therein having the cover on the first opposing open end portion with a second sub-composite including at least one dielectric layer such that the cover faces the second sub-composite, positioning a layer of heat-deformable dielectric material between the first and second sub-composites, and bonding the first and second sub-composites and layer dielectric material together using heat and/or pressure sufficient to deform the layer of heat-deformable material, the cover on the at least one opening preventing the dielectric material of the layer of heat-deformable dielectric material from entering the opening.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-5 illustrate the steps of making a PCB according to one aspect of the invention, each of these FIGS being an elevational view, in section;

FIG. 6 is also an elevational view, in section, illustrating the positioning of a pinned electrical component within the PCB made using the steps of FIGS. 1-5, to form an electrical assembly; and

FIG. 7 is an elevational view, in section, showing a PCB according to an alternative embodiment of the invention, this PCB having a pinned electrical component positioned therein.

BEST MODE FOR CARRYING OUT THE INVENTION

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. It is understood that like numerals will be used to indicate like elements from FIG. to FIG.

As stated above, the term “high speed” as used herein is meant signals of high frequency. Examples of such signal frequencies attainable for the multilayered PCBs defined herein and as produced using the methods taught herein include those within the range of from about 3.0 to about 10.0 gigabits per second (GPS). These examples are not meant to limit this invention, however, because frequencies outside this range, including those higher, are attainable. As further understood from the following, the PCB products produced herein are formed of at least two separate multilayered portions (sub-composites) which have themselves been formed prior to bonding to each other. At a minimum, each of these sub-composites will include at least one dielectric layer and at least one thru-hole” therein, with most likely embodiments including more than one dielectric layer and usually more then one internal conductive layer, in addition to more than one thru-hole. Examples are provided below and are just that (only examples) and the numbers of layers shown and described are not meant to limit the scope of this invention.

As also stated above, the term “thru-hole” is meant to include conductive holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as “internal vias” (sometimes referred to as “buried vias”) which is internally “captured” by the board's outer layers.

Examples of dielectric materials usable for dielectric layers in the sub-composites taught herein include the aforementioned fiberglass-reinforced epoxy resins (some referred to simply as “FR4” dielectric materials in the art, for the flame retardant (FR) rating of same), polytetrafluoroethylene (e.g., Teflon), and Driclad dielectric material. In addition, polyimides, polyamides, cyanate resins, photo-imageable materials, and other like materials may also be utilized. Examples of conductor materials usable for the conductor layers used in such sub-composites include copper or copper alloys, but may include or comprise additional metals (e.g., nickel, aluminum, etc.) or alloys thereof. Such conductor materials are used to form these layers, which in turn may serve as power, signal and/or ground layers. If as a signal layer, several conductor lines and/or pads may constitute the layer, while if used as power or ground, such layers will typically be of substantially solid construction. Combinations of signal, power and/or ground are possible in one layer.

The resulting multilayered PCBs defined herein are particularly adapted for use in what can be defined as “information handling systems”. By the term “information handling system” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc. Understandably, the substrates herein are also adaptable for use in other environments and are not limited to such usage.

By the term “electrical component” as used herein is meant components having pinned connections which project there-from and are adapted for being positioned within receptive holes of a PCB. The most notable example of such a component in an electrical connector which typically includes an electrically insulating housing with a plurality of contacts therein and a plurality of pins extending from the housing for hole placement. The invention is not so limited, however, because the PCBs produced in accordance with the present teachings are adapted for receiving pins and the like from any electrical component having same. Although this invention is particularly adapted for use with pinned components, other components such as conventional surface mount, ball grid array (BGA), land grid array (LGA) and the like may be used on the finished PCB surfaces.

By the term “electrical assembly” as used herein is meant at least one PCB as defined herein in combination with at least one electrical component as defined above electrically coupled thereto and forming part of the assembly.

Finally, by the term “sub-composite” as used herein is meant a structure including at least one dielectric layer. In at least one instance, this term is also meant to define such a structure with at least one thru-hole therein, the thru-hole having an open portion on at least one end thereof which is exposed at the corresponding outer surface of the dielectric. Examples are defined in greater detail herein-below.

In FIG. 1, there is seen a first sub-composite 21 according to one embodiment of the invention. Sub-composite 21 includes at least one dielectric layer 23 (actually, three such layers are shown in this structure) and at least one thru-hole 25 which extends through the entire sub-composite thickness. Preferably, several such thru-holes are utilized, and in one embodiment, as many as 50,000 or more may be formed. The preferred dielectric material is one of those described above, and, as stated, three layers are used for this particular embodiment. In other embodiments, as many as twenty or more such dielectric layers may be used, so the invention is not limited to any specific number of same. In the sub-composite of FIG. 1, there are at least two conductive layers 27 and 29, although the invention is not limited to this number. The preferred conductive material for layers 27 and 29 is copper or copper alloy. In its most simple form, sub-composite 21 need not include any internal conductive layers. In one embodiment (where the aforementioned twenty dielectric layers may be used), a total of nineteen conductive layers may be also used, these dielectric and conductive layers alternatively positioned in the structure. These conductive layers may be in several forms. Some may each comprise a plurality of signal conductors which occupy a plane (as shown by layer 27), or may be in the form of a substantially solid planar member (as shown by layer 29), if used as a power or ground plane in the final PCB. Alternative layer structures, including one which includes both signal conductors and a ground or power portion, are possible and further description is not considered necessary.

In the FIG. 1 embodiment, layer 27, as stated, is preferably a signal layer including spaced conductors (e.g., lines) 31, while layer 29 is preferably a ground plane with “clearance” openings 33 therein. Such “clearance” openings are known and designed to allow smaller diameter conductive thru-holes to pass there-through.

Sub-composite 21 as shown in FIG. 1 is preferably formed by providing a first dielectric layer (i.e., 23′), bonding a conductive layer (i.e., 29) thereto and subjecting the conductive layer to photolithographic processing to form the desired number of clearance openings. A second dielectric layer 23″ is then positioned atop the now patterned layer 29 and bonded, e.g., laminated, thereto. The next conductive layer 27 is then bonded to this dielectric layer and also patterned, again preferably using conventional photolithographic processing known in the PCB industry. Thereafter, the final dielectric layer 23 is then bonded, e.g., laminated, to the patterned signal layer. Alternatively, this same sub-composite 21 can be formed in a parallel manner, whereby cores using dielectric layers 23 and 23′ are formed simultaneously (in parallel), and then these cores are bonded together with interim dielectric layer 23″. An opening 34 (actually, the total number desired) is (are) then formed, e.g., using mechanical or laser drilling (in one embodiment, an ultraviolet Nd:YAG laser may be used; alternatively, a CO² or excimer laser may be used) within this “sandwich” and conductive material 35, e.g., copper or copper alloy, deposited on the internal walls of the opening(s). Such deposition is preferably accomplished using electroplating, either electrolytic or electro-less plating, both processes also known in the PCB industry. Prior to such processing, it may be necessary to provide a “seed” layer on the dielectric surfaces for better copper adhesion. The resulting structure is a PTH-type of thru-hole 37 as defined above, having conductive internal walls and opposing “land” portions 38 which lie atop the opposing exterior surfaces of sub-composite 21. Sub-composite 21 is now ready for the next step in the inventive process taught herein.

In FIG. 2, a pair of sub-composites 21 and 41 is provided, each substantially similar in construction in that each includes at least one and preferably several (e.g., the number mentioned above) of thru-holes 37 therein. By similar is not meant identical as each sub-composite may include more or fewer conductive layers and thru-holes. In one embodiment, for reasons explained below, the lower sub-composite 41 may not include any thru-holes therein. It may, however, include several conductive inner layers, two being shown in FIG. 2 and represented by the numerals Next, each of the thru-holes are “capped” with a cover member 43 on the open end thereof (and atop the land) facing the other sub-composite. This capping is preferably accomplished using a dry film solder mask material, one example sold under the product name “LB404” by Morton International, Chicago, Ill. This dry film is positioned on the respective surfaces of the sub-composite and covers the exposed open ends of the thru-holes therein. Photolithographic processing is then used to define the ultimate pattern of individual solder mask covers for each of the open ends that will remain in place. Undesirable dry film is “developed” out and removed using conventional processing. The result is that selected ones of the thru-holes include a cover 43 thereon, as shown in FIG. 2. In one example, the land and cover together possessed a thickness (T1) of about four mils (0.004″). In the next step, a dielectric layer 51, preferably a conventional “sticker sheet” used in PCB manufacturing, is positioned between the pair of sub-composites. A preferred material for this interim dielectric material is the aforementioned Driclad material produced and sold by the Assignee of this invention, Endicott Interconnect Technologies, Inc. In one embodiment, this dielectric layer possesses a thickness of about six mils (0.006″), which is, significantly, thicker than the corresponding thicknesses (T1) of the thru-hole land-cover structures. The dielectric layer 51 may further include openings (two shown in FIG. 2), each of which is aligned with a corresponding thru-hole land-cover structure of one of the two sub-composites 21 or 41. This alignment relative to such structures in the bonded sub-composites is also shown in FIGS. 3-7.

The two sub-composites 21 and 41 and the interim dielectric layer 51 are now bonded together, preferably using conventional lamination. In one example, the lamination process was conducted at a temperature within the range of from about 180 degrees Celsius (hereinafter also simply referred to as C) to about 200 degrees C., and at a pressure within the range of from about 100 pounds per square inch (hereinafter also simply referred to as PSI) to about 700 PSI. During this lamination, the heat of the process causes the interim layer 51 to deform, meaning that is softens and is compressible to the extent that it “flows” laterally under compression. Significantly, providing layer 51 of a greater thickness than the corresponding land-cover thicknesses T1 enables the interim layer to prevent the deformed material from entering the thru-holes, while still assuring the effective compression of the entire sub-composite and interim layer sub-assembly. In the finally laminated structure, shown in FIG. 3, layer 51 is compressed to a thickness of from about four mils (0.004″) to about five mils (0.005″). Significantly, none of its material has entered any of the thru-holes.

In the steps shown in FIGS. 4 and 5, at least one (preferably several) opening 53 is (are) formed within the bonded sub-assembly and then rendered conductive. In one embodiment, a total of 50,000 or more openings 53 may be formed, preferably using mechanical or laser drilling, with each having a diameter of about twenty-two mils (0.022″). Significantly, the opening 53 in FIGS. 4 and 5 passes through the “clearance” openings in the layers 29 and does not, therefore, become electrically coupled thereto when the internal walls of the opening are rendered conductive. Such conductivity is preferably accomplished using electroplating, preferably the same process used to provide the conductive layers 35 for the openings in sub-composites 21 and 41. The conductive material on the walls of opening 53 is represented by the numeral 55. In one embodiment, this material, preferably copper or copper alloy (and possibly also including additional metallurgy such as nickel and/or gold) has a total thickness of about one mil (0.001″), leaving an internal open diameter for the opening of about twenty mils (0.020″). This compares to the similar internal open diameter of thru-holes 37. With such conductive material now in place, opening 53 is now also a thru-hole as defined in one embodiment above.

The resulting sub-assembly shown in FIG. 5 is now understood to be a multilayered printed circuit board, having a desired number of conductive layers and dielectric layers therein and, significantly, a plurality of different length thru-holes, none of which include adverse material such a fiber-glass shards or projecting ends or dielectric resin itself therein. Such materials understandably may interfere with the effective connectivity of the board's thru-holes with additional components when positioned therein. One such electrical component is shown in FIG. 6 and represented by the numeral 61. In one embodiment, component 61 is an electrical connector with a plurality of pins 63 projecting there-from. Pinned electrical connectors are known in the electronics art and further description is not considered necessary. In one embodiment, the connector may be a connector sold by FCI, having a business location in Harrisburg, Pa., USA, under the product name Airmax VS. The AirMax VS connector exhibits excellent signal integrity at speeds from 2.5 Gb/s to 6.25 Gb/s, with low insertion losses. The pins of this connector each have an outer diameter of 20 mils (0.020″), meaning that these may be effectively inserted within the thru-holes and electrically coupled thereto. In the FIG. 6 embodiment, the pin on the left is understood to also be coupled to the signal conductor 31 shown in turn as being coupled to the internal conductive material of thru-hole 37 while the pin on the right is shown as coupled within the longer length thru-hole to the lowermost signal conductor shown, 31, in sub-composite 41, because this conductor is also electrically coupled to the conductive material of the longer thru-hole. These connections are understood to be representative only as several other combinations are well within the scope of this invention, including coupling one or more pins to a ground layer (i.e., if instead the upper layer 29 in sub-composite 21 were directly electrically coupled to one of the thru-holes).

The resulting electrical assembly shown in FIG. 6 is now adapted for being positioned with a housing (not shown) of an information handling system (e.g., personal computer, server, mainframe) or other system and thus function as part of this structure's electrical system. These information systems are well known in the art and further description is not considered necessary.

In the FIG. 6 embodiment, it is understood that the printed circuit board is capable of receiving pinned electrical components from both opposing sides. Thus, component 61 could be inserted within the board from the underside instead of from the top as shown, or, if appropriate pin lengths were used, from both sides, with one pin sharing the common elongated thru-hole in the center. Understandably, with several combinations of partial depth thru-holes extending within the board, and several elongated thru-holes also being formed, electrical components may be inserted from opposite sides without common thru-hole sharing. As stated above, the lower sub-composite does not need to include any partial depth thru-holes. The FIG. 6 embodiment is thus meant to illustrate that additional capabilities of the invention are readily possible.

The embodiment of FIG. 7 is of similar initial construction as the structure of FIG. 6 with the exception that no thru-holes are shown as being formed within the lower sub-composite, referenced by the numeral 41′. It is understood that such thru-holes may be provided, of course, if opposite side component positioning is desired. These are now shown in FIG. 7 for ease of illustration. The FIG. 7 embodiment includes a third sub-composite, referenced by numeral 71, which, as shown, may include internal conductive layers therein, as do sub-composites 21 and 41′. The board structure is formed by first bonding sub-composites 21 and 41′, as was done for sub-composites 21 and 41, following which the second thru-hole is formed and extends through both bonded sub-composites. This second thru-hole is then capped (covered with cover 43) and the third sub-composite bonded to this structure. The cover prevents material from the interim “sticker sheet” from entering the thru-hole, as did covers 43 above. With all three sub-composites now bonded together, an opening is formed through the entire thickness of the structure, and then plated as was opening 53 for the FIG. 6 embodiment. This opening, now a thru-hole 81, is understandably the opening to the right in FIG. 7, and, as shown, is longer than the other two openings, including the elongated opening immediately adjacent thereto. The board structure of FIG. 7 is thus capable of accepting yet another pin (now shown as pin 63′) from an electrical component, thereby further illustrating the added versatility of the invention. As with the embodiment above, this longer opening may also serve as a common opening for two opposing pins, or, if provided in plural, as an individual thru-hole for a pin from either side (including the embodiment where the other side also includes partial depth thru-holes therein, as explained above. The longest thru-hole may also be electrically coupled to one or more of the conductive planes, depending on the operational requirements for the finished board. In the FIG. 7 embodiment, the thru-hole on the right is shown as being electrically coupled to the lower signal conductor (that to the lower, right) within sub-composite 71. Again, several other combinations of such connections are well within the scope of this invention.

Thus there has been shown and described a new and unique method of making a printed circuit board in which openings of different length are formed which do not include dielectric material therein such that the openings may receive pins from an electrical component inserted therein and be electrically coupled thereto so that the pins may make contact with selected conductive elements within and/or upon the board. The formed board is capable of having electrical components inserted from both sides thereof, with relatively minor modification to the process. The resulting board is capable of passing high speed signals. The invention thus represents a significant advancement in the art.

While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A method of making a multilayered printed circuit board (PCB), said method comprising: providing a first sub-composite including at least one dielectric layer and at least one opening therein having first and second opposing open end portions and extending substantially through said at least one dielectric layer; positioning a cover on said first opposing open end portion of said at least one opening; aligning said first sub-composite having said at least one opening therein having said cover on said first opposing open end portion with a second sub-composite including at least one dielectric layer such that said cover faces said second sub-composite; positioning a layer of heat-deformable dielectric material between said first and second sub-composites; and bonding said first and second sub-composites and said layer of heat-deformable dielectric material together using heat and/or pressure sufficient to deform said layer of heat-deformable material, said cover on said first open end portion of said at least one opening preventing said dielectric material of said layer of heat-deformable dielectric material from entering said at least one opening.

2. The method of claim 1 further including forming a second opening within said first and second sub-composites when said sub-composites are bonded, said second opening extending substantially through said first and second sub-composites and being longer than said at least one opening.

3. The method of claim 2 wherein said forming of said second opening within said first and second sub-composites is accomplished using a laser.

4. The method of claim 2 wherein said at least one opening is provided as a first conductive thru-hole prior to said positioning of said cover, said method further including providing a conductive material on the internal walls of said second opening to form at least a second conductive thru-hole within said bonded first and second sub-composites.

5. The method of claim 4 further including providing an electrical component having at least two pins extending there-from and inserting a first of said pins within said first conductive thru-hole and a second of said pins within said at least one second conductive thru-hole to form an electrical assembly.

6. The method of claim 5 further including positioning said electrical assembly within a housing to form an information handling system.

7. The method of claim 5 wherein said providing said conductive material on said internal walls of said second opening is accomplished using an electroplating operation.

8. The method of claim 1 further including providing each of said first and second sub-composites with at least one electrically conductive layer therein.

9. The method of claim 8 further including forming circuitry as at least part of said electrically conductive layers.

10. The method of claim 1 wherein said positioning of said cover on said first opposing open end portion of said at least one opening is accomplished using solder-mask material.

11. The method of claim 10 wherein said solder-mask material is provided in the form of a continuous layer and positioned on said first sub-composite, selected portions of said continuous layer of said solder-mask material thereafter being removed such that only the remaining portion thereof covers said at least one opening.

12. The method of claim 1 wherein said bonding of said first and second sub-composites and said layer dielectric material together using said heat and/or pressure sufficient to deform said layer of heat-deformable material is accomplished using a lamination process.

13. The method of claim 1 further including providing an opening with said layer of heat-deformable dielectric material and aligning said opening within said layer of heat-deformable material with said at least one opening within said first sub-composite and said cover positioned on said first opposing open end portion of said at least one opening during said bonding of said first and second sub-composites.