The present disclosure relates to a method of manufacturing a redistribution layer, a redistribution layer and an integrated circuit including the redistribution layer.
As is known, integrated circuits (ICs) are composed of several overlapping layers made of semiconducting, insulating and conductive materials, typically defined by photolithography.
In a first phase (front end of line, FEOL) of a manufacturing process of an integrated circuit, individual devices such as, among others, transistors, diodes, resistors and capacitors, are patterned in and on the surface of a wafer.
In a second phase (back end of line, BEOL), the individual devices are interconnected by conductive metal lines. In particular, due to the complexity of modern IC layouts and high density of individual devices, the back end of line process comprises manufacturing several stacked metal layers, electrically insulated from one another by dielectric layers; vias through the dielectric layers allow connecting any metal layer to the metal layers below and/or the one above.
In a third phase of the IC manufacturing process, a redistribution layer (RDL) is patterned above the last metal interconnection layer. As is known, the redistribution layer is an extra metal layer used for routing the input/output pads to other locations on the die area, enabling simpler chip-to-chip bonding.
The IC 1 includes an interconnection layer 3, made of conductive material; the redistribution layer 2 includes a dielectric layer 4 extending above the interconnection layer 3 and a first passivation layer 6 extending above the dielectric layer 4.
The redistribution layer 2 further comprises a barrier region 8, extending above a top surface 6a of the first passivation layer 6 and across the whole depth of the first passivation layer 6 and of the dielectric layer 4, so as to be in contact with the interconnection layer 3.
The redistribution layer 2 further comprises a conductive region 10, extending on top of the barrier region 8. In particular, in a top view of the IC 1, the conductive region 10 is extending only inside the area defined by the barrier region 8. As a consequence, the conductive region 10 is not in contact with the first passivation layer 6.
Moreover, the thickness of the barrier region 8 is lower than the sum of the thicknesses of the dielectric layer 4 and of the first passivation layer 6. As a consequence, a part of the conductive region 10 extends below the top surface 6a of the first passivation layer 6. In other words, the barrier region 8 and the conductive region 10 form a via through the dielectric layer 4 and the first passivation layer 6, providing a conductive path from the interconnection layer 3 to the top surface 6a of the first passivation layer 6.
The redistribution layer 2 further comprises a first coating region 12, extending above the first passivation layer 6, around the conductive region 10 and the barrier region 8, and above the conductive region 10. The first coating region 12 is in contact with the top surface 6a of the first passivation layer 6, the conductive region 10 and the barrier region 8. In other words, the first coating region 12 completely covers the portions of the barrier region 8 and of the conductive region 10 extending above the top surface 6a of the first passivation layer 6.
The redistribution layer 2 further comprises a second coating region 14, extending above the first passivation layer 6, around the first coating region 12 and above the first coating region 12. The second coating region 14 is in contact with the first passivation layer 6 and the first coating region 12. In other words, the second coating region 14 completely covers the first coating region 12.
The redistribution layer 2 further comprises a second passivation layer 16 (e.g., polyimide, lead oxide (PbO), epoxy, etc.), extending above the first passivation layer 6 and around the second coating region 14.
In particular, a convenient choice of conductive materials for the redistribution layer 2 is such that the conductive region 10 is made of copper (Cu), the first coating region 12 is made of nickel (Ni) and the second coating region 14 is made of palladium (Pd).
In particular, the choice of nickel and palladium as a finishing stack on the conductive region 10 is due to its well-known advantages over aluminum as a bonding surface for copper wires, for instance in terms of bond window, shear strength, pad damage and reliability.
A known drawback of the redistribution layer 2 according to the prior art is due to an issue of the typically employed manufacturing method, which involves an electroless growth of nickel over copper, in order to form the first coating region 12 around and above the conductive region 10. Typically, at the end of this step, the first coating region 12 is not completely in contact with the top surface 6a of the first passivation layer 6, and a small gap of the order of few nanometers may exist between the first coating region 12 and the first passivation layer 6.
As a consequence, the nickel surface is not completely sealed, remaining exposed to environmental conditions. As is known, in presence of high temperature and high moisture rate, the nickel surface can be affected by corrosion processes. Moreover, it is known that high electric fields can lead to the formation of dendritic structures able to electromigrate and give rise to electrical shorts between two nickel lines, eventually leading to an IC failure.
An aim of the present disclosure is to provide a method of manufacturing a redistribution layer, a redistribution layer and an integrated circuit including the redistribution layer, to overcome the problems previously illustrated. In particular, one of the aims of the present disclosure is to completely seal the nickel surface in a copper redistribution layer with Ni/Pd finishing.
According to the present disclosure, a method of manufacturing a redistribution layer, a redistribution layer and an integrated circuit including the redistribution layer are provided.
For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:
The IC 21 includes an interconnection layer 23, made of conductive material, such as aluminum or copper. In particular, the interconnection layer 23 is the last metal line of the BEOL of IC 21.
The redistribution layer 22 comprises a dielectric layer 24 extending above the interconnection layer 23 and a first passivation layer 26 extending above the dielectric layer 24. In the following, the term “insulating layer” refers to the stack composed of the dielectric layer 24 and the first passivation layer 26.
In particular, the dielectric layer 24 is made of an insulating material, such as silicon dioxide (SiO2), and has thickness comprised for instance between 900 nm and 1200 nm.
In particular, the first passivation layer 26 is made of an insulating material, such as silicon nitride (Si3N4), and has thickness comprised for instance between 500 nm and 650 nm. The first passivation layer 26 is delimited by a top surface 26a and a bottom surface 26b, the bottom surface 26b being in contact with the dielectric layer 24.
The redistribution layer 22 further comprises a barrier region 28. A first portion of the barrier region 28 extends above the top surface 26a of the first passivation layer 26; a second portion of the barrier region 28, in contact with the first portion, extends below the top surface 26a of the first passivation layer 26, and across the whole depth of the first passivation layer 26 and of the dielectric layer 24, so as to be in contact with the interconnection layer 23.
The redistribution layer 22 further comprises a conductive region 30, extending on top of the barrier region 28. In particular, in a top view of the IC 21, not shown in the figures, the conductive region 30 is extending only inside the area defined by the barrier region 28. As a consequence, the conductive region 30 is not in contact with the first passivation layer 26. In the following, the term “conductive body” refers to the stack composed of the barrier region 28 and the conductive region 30.
Moreover, the thickness of the barrier region 28 is lower than the combined thickness of the dielectric layer 24 and the first passivation layer 26. As a consequence, a portion of the conductive region 30 extends below the top surface 26a of the first passivation layer 26. In other words, the barrier region 28 and the conductive region 30 form a via through the dielectric layer 24 and the first passivation layer 26, providing a conductive path from the interconnection layer 23 to the top surface 26a of the first passivation layer 26, extending further above the top surface 26a of the first passivation layer 26.
In particular, the barrier region 28 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), and has thickness comprised for instance between 270 nm and 330 nm.
In particular, the conductive region 30 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.
The redistribution layer 22 further comprises a first coating region 32, extending above the conductive region 30 and around the conductive region 30, in correspondence of sidewalls of the portion of the conductive region 30 above the top surface 26a of the first passivation layer 26.
In particular, the first coating region 32 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.
According to an aspect of the present disclosure, the first coating region 32 is not in contact with the first passivation layer 26. In particular, the portion of the first coating region 32 extending around the sidewalls of the conductive region 30 has a surface 32a directly facing the top surface 26a of the first passivation layer 26 and substantially parallel to the top surface 26a of the first passivation layer 26, at a distance Hgap from the top surface 26a of the first passivation layer 26, said distance being comprised for instance between 10 nm and 50 nm (in particular, 25 nm) when measured along the z axis.
The redistribution layer 22 further comprises a second coating region 34, extending above the first passivation layer 26, around the first coating region 32 and above the first coating region 32. The second coating region 34 is in contact with the first passivation layer 26 and the first coating region 32. In other words, the second coating region 34 completely covers the first coating region 32.
In particular, the second coating region 34 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.
According to an aspect of the present disclosure, the second coating region 34 extends between the first passivation layer 26 and the first coating region 32, filling a gap having height Hgap between the first passivation region 26 and the first coating region 32. In other words, the second coating region 34 completely seals the first coating region 32. As a consequence, differently from the case of the redistribution layer 2 of
The redistribution layer 22 further comprises a second passivation layer 36, extending above the first passivation layer 26 and around the second coating region 34. In particular, the second passivation layer 36 is made of an insulating material, such as polyimide, PbO, epoxy, etc.
As is clear from
Moreover, the IC 21 comprises further metal interconnection layers, insulating layers and vias formed in the BEOL extending below the interconnection layer 23 and collectively designated with the reference numeral 50. In addition, the IC 21 includes a semiconductor substrate 51 in which are formed circuit elements, such as transistors, diodes, resistors and capacitors.
With reference to
A dielectric layer 64 is formed above the interconnection layer 63. In particular, the dielectric layer 64 is made of an insulating material, such as silicon dioxide (SiO2), and has thickness comprised for instance between 900 nm and 1200 nm.
A first passivation layer 66 is formed above the dielectric layer 64. In particular, the first passivation layer 66 is made of an insulating material, such as silicon nitride (Si3N4), and has thickness comprised for instance between 500 nm and 650 nm. In the following, the term “insulating layer” refers to the stack composed of the dielectric layer 64 and the first passivation layer 66.
Then,
Then,
In particular, the barrier layer 68 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN). Moreover, the thickness of the barrier layer 68 is lower than the combined thickness of the dielectric layer 64 and the first passivation layer 66, and in particular is comprised for instance between 270 nm and 330 nm. Then, a seed layer 69 is formed above the barrier layer 68, partially filling the trench 67. For instance, the seed layer 69 is deposited by PVD.
In particular, the seed layer 69 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 180 nm and 220 nm, such that the trench 67 is only partially filled by the seed layer 69.
Then,
In particular,
Then,
In particular, the conductive layer 70 is made of the same conductive material of the seed layer 69, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.
In particular, the conductive layer 70 is formed by electrodeposition. Then, the photolithography mask 70′ is removed by a wet removal process, exposing portions of the seed layer 69 not covered by the conductive layer 70.
Then,
Then, the exposed portions of the barrier layer 68 are removed, for instance by wet etching, up to exposing the portions of the first passivation layer 66 underneath, without affecting the portions of the barrier layer 68 below the conductive layer 70, for instance by employing standard photolithography techniques. As a consequence, the barrier region 28 of the redistribution layer 22 of
Then,
In particular, the first coating layer 72 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.
Then,
According to an aspect of the present disclosure, the thermal treatment comprises a first step of increasing the temperature of the wafer 60 from room temperature to a high temperature. Room temperature is comprised for instance between 20° C. and 25° C.; the high temperature is comprised for instance between 245° C. and 255° C. In particular, the increase in temperature occurs during a first time interval, comprised for instance between 10 s and 60 s.
Then, in a second step, following the first step of the thermal treatment, the wafer is kept at the high temperature for a second time interval comprised for instance between 30 s and 180 s.
Then, in a third step, following the second step of the thermal treatment, the temperature of the wafer 60 is decreased from the high temperature to room temperature over a third time interval, for example, lasting no more than 180 s.
In particular, while applying the thermal treatment, the wafer 60 is kept in a nitrogen (N2) atmosphere at a pressure comprised between 1.0 and 5.0 Torr.
The Applicant verified that by applying to the wafer 60 the thermal treatment described above, some mechanical properties of the barrier layer 68, of the conductive layer 70 and of the first coating layer 72 can be conveniently modified. In particular, the coefficient of thermal expansion and the Young modulus are modified with the thermal treatment, and the residual stress of said layers is modified, resulting, at the end of the thermal treatment, in the formation of the gap 73.
Then,
In particular, the second coating layer 74 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.
Then, a second passivation layer is formed above the first passivation layer 26 and around the second coating region 94. In particular, the second passivation layer is made of an insulating material, such as polyimide. Thus, the redistribution layer 22 of
The Applicant verified that a possible issue of the redistribution layer 22 of
The redistribution layer 82 differs from the redistribution layer 22 of
In particular, the spacers 86 are of insulating material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), and have a thickness Hgap2 comprised for instance between 10 nm and 100 nm (in particular, 25 nm).
The redistribution layer 82 further comprises a barrier region 88, extending above the spacers 86 and across the whole depth of the first passivation layer 26 and of the dielectric layer 24, so as to be in contact with the interconnection layer 23.
The redistribution layer 82 further comprises a conductive region 90, extending on top of the barrier region 88. In particular, in a top view of the IC 81, not shown in the figures, the conductive region 90 is extending only inside the area defined by the barrier region 88. As a consequence, the conductive region 90 is not in contact with the first passivation layer 26. In the following, the term “conductive body” refers to the stack composed of the barrier region 88 and the conductive region 90.
Moreover, the thickness of the barrier region 88 is lower than the combined thickness of the dielectric layer 24 and of the first passivation layer 26. As a consequence, a part of the conductive region 90 extends below the top surface 26a of the first passivation layer 26. In other words, the barrier region 88 and the conductive region 90 form a via through the dielectric layer 24 and the first passivation layer 26, providing a conductive path from the interconnection layer 23 to the top surface 26a of the first passivation layer 26.
In particular, the barrier region 88 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), and has thickness comprised for instance between 270 nm and 330 nm.
In particular, the conductive region 90 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.
The redistribution layer 82 further comprises a first coating region 92, extending above the conductive region 90 and around the conductive region 90, in correspondence of sidewalls of the portion of the conductive region 90 above the top surface 26a of the first passivation layer 26. In other words, the first coating region 92 covers the surface of the conductive region 90 not already covered by the barrier region 88.
In particular, the first coating region 92 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.
According to an aspect of the present disclosure, the first coating region 92 is not in contact with the first passivation layer 26. In particular, the portion of the first coating region 92 extending around the sidewalls of the conductive region 90 has a surface 92a directly facing the top surface 26a of the first passivation layer 26 and substantially parallel to the top surface 26a of the first passivation layer 26, at a distance Hgap2 from the top surface 26a of the first passivation layer 26 being equivalent to the height Hgap2 of the spacers 86, said distance Hgap2 being measured along the z axis.
The redistribution layer 22 further comprises a second coating region 94, extending above the first passivation layer 26, around the first coating region 92 and above the first coating region 92. The second coating region 94 is in contact with the first passivation layer 26 and the first coating region 92. In other words, the second coating region 94 completely covers the first coating region 92.
In particular, the second coating region 94 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.
According to an aspect of the present disclosure, the second coating region 94 extends between the first passivation layer 26 and the first coating region 92, filling a gap between the first passivation region 26 and the first coating region 92. In other words, the second coating region 94 completely seals the first coating region 92. As a consequence, as in the case of the redistribution layer 22 of
With reference to
A dielectric layer 104 is formed above the interconnection layer 103. In particular, the dielectric layer 104 is made of an insulating material, such as silicon dioxide (SiO2), and has thickness comprised for instance between 900 nm and 1200 nm.
A first passivation layer 106 is formed above the dielectric layer 104. In particular, the first passivation layer 106 is made of an insulating material, such as silicon nitride (Si3N4), and has thickness comprised for instance between 500 nm and 650 nm. In the following, it will be used the term “insulating layer” to refer to the stack composed of the dielectric layer 104 and the first passivation layer 106.
A spacing layer 105 is formed above the first passivation layer 106. In particular, the spacing layer 105 is made of an insulating material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).
According to an aspect of the present disclosure, the spacing layer 105 is employed as a sacrificial layer, being partially etched in a following step of the method of manufacturing. For this reason, preferably, the spacing layer 105 has a high selectivity in terms of etching with respect to the first passivation layer 106. As a consequence, the choice of the material employed for the spacing layer 105 depends on the material employed for the first passivation layer 106. For instance, if the first passivation layer 106 is made of Si3N4, the spacing layer 105 is preferably made of SiO2 or of a high etch-rate Si3N4. As is known, a higher etch-rate Si3N4 can be obtained by depositing the spacing layer 105 at a lower temperature than the one employed for depositing the first passivation layer 104. In particular, the spacing layer 105 has the thickness Hgap2.
Then,
Then, a barrier layer 108 is formed above the spacing layer 105, for instance by PVD. The barrier layer 108 partially fills the trench 107, covering the previously exposed sidewalls of the spacing layer 105, of the first passivation layer 106 and of the dielectric layer 104, and covering the previously exposed surface of the interconnection layer 103.
In particular, the barrier layer 108 is made of conductive material, such as titanium (Ti), titanium-tungsten (TiW), or titanium nitride TiN). Moreover, the thickness of the barrier layer 108 is lower than the combined thickness of the dielectric layer 104, the first passivation layer 106 and the spacing layer 105, and in particular is comprised for instance between 270 nm and 330 nm. Then, a seed layer 109 is formed above the barrier layer 108, partially filling the trench 107. For instance, the seed layer 109 is deposited by PVD.
In particular, the seed layer 109 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 180 nm and 220 nm, such that the trench 107 is only partially filled by the seed layer 109.
Then, a photolithography mask (not shown in the figures) is applied at the exposed surface of the seed layer 109. In particular, the layout of the photolithography mask is designed considering that openings in the mask define areas in which a layer will be formed in a following step of the manufacturing method.
In particular, the photolithography mask presents an opening in correspondence of the partially filled trench 107.
Then,
In particular, the conductive layer 110 is made of the same conductive material of the seed layer 109, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.
In particular, the conductive layer 110 is formed by electrodeposition. Then, the photolithography mask is removed by a wet removal process, exposing portions of the seed layer 109 not covered by the conductive layer 110.
Then, said exposed portions of the seed layer 109, not covered by the conductive layer 110, are removed, for instance by wet etching, up to exposing the portions of the barrier layer 108 underneath. Thus, the remaining portions of the seed layer 109, covered by the conductive layer 110, form, together with the conductive layer 110, the conductive region 90 of the redistribution layer 82 of
Then, the exposed portions of the barrier layer 108 are removed, for instance by wet etching, up to exposing the portions of the spacing layer 105 underneath, without affecting the portions of the barrier layer 108 below the conductive layer 110. As a consequence, the barrier region 88 of the redistribution layer 82 of
Then,
In particular, the first coating layer 112 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.
Then,
In particular, the spacing layer 105 is etched by wet etching, using chemicals that remove the spacing layer 105 selectively with respect to the first coating layer 112, the barrier layer 108 and the first passivation layer 106.
For instance, the wafer 100 can be immersed in a hydrofluoric (HF) acid bath on in a buffered hydrofluoric (BHF) batch if the spacing layer 105 is made of silicon dioxide or a high etch rate silicon nitride, so that the spacing layer 105 is etched at a faster rate than the surrounding layers.
In particular, the etching step proceeds at least until the gap 113 is completely formed, so that the remaining portions of the spacing layer 105 do not extend between the first passivation layer 106 and the first coating layer 112. In other words, at the end of the etching step of
Then,
In particular, the second coating layer 114 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.
Then, a second passivation layer is formed above the first passivation layer 106 and around the second coating region 114. In particular, the second passivation layer is made of an insulating material, such as polyimide. Thus, the redistribution layer 82 of
The advantages of the disclosure described previously, according to the various embodiments, emerge clearly from the foregoing description.
In particular, since the first coating region is completely sealed by the second coating region, it is possible to use materials for the first coating region that are subject to corrosion when exposed to the environment, without compromising the reliability of the redistribution layer.
The full sealing of the conductive material can also improve the electromigration performances of the device.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Number | Date | Country | Kind |
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102018000007967 | Aug 2018 | IT | national |
102018000007968 | Aug 2018 | IT | national |