Patent Application
20250038059
The present application generally relates to semiconductor technology, and more particularly, to a modular interconnection unit, a semiconductor package, and a method for making the same.
The semiconductor industry is constantly faced with complex integration challenges as consumers want their electronics to be smaller, faster and higher performance with more and more functionalities packed into a single device. One of the solutions is Package-on-Package (POP). PoP is a type of packaging method that combines two or more integrated circuit (IC) packages together. In a typical PoP, two or more packages are vertically connected (i.e., stacked) via vertical interconnection units that can direct signals between them. A POP assembly can more efficiently use space, and reduce lengths of signal paths between the packages. Thus, a better electrical performance can be achieved, as the shorter signal path length may reduce noises and cross talks in integrated circuits and promote faster signal response. However, the process for forming the POP assembly is complex, and the yield is still low.
Therefore, a need exists for improvements to the manufacturing method of semiconductor packages.
An objective of the present application is to provide a method for making a semiconductor package with higher reliability.
According to an aspect of the present application, a method for forming a semiconductor package is provided. The method may include: providing a first sub-package including a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on an upper surface of the first substrate; mounting at least one modular interconnection unit on the upper surface of the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and raised from an upper surface of the dielectric layer, and a protection layer covering the conductive bump and having a flat upper surface, and wherein the conductive via is electrically coupled with the first interconnection pattern; forming a first encapsulant on the upper surface of the first substrate to encapsulate the first electronic component and the modular interconnection unit; removing a portion of the protection layer to expose an upper surface of the conductive bump; and mounting a second sub-package above the first encapsulant, wherein the second sub-package includes a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on an upper surface of the second substrate, and the second interconnection pattern is electrically coupled with the conductive bump.
According to another aspect of the present application, a semiconductor package is provided. The semiconductor package may include: a first sub-package including a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on an upper surface of the first substrate; at least one modular interconnection unit mounted on the upper surface of the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and raised from an upper surface of the dielectric layer, and a protection layer disposed on the dielectric layer and partially covering the conductive bump, wherein the conductive via is electrically coupled with the first interconnection pattern, and wherein an upper surface of the conductive bump is exposed from the protection layer; a first encapsulant disposed on the upper surface of the first substrate, wherein the first encapsulant surrounds the first electronic component and the modular interconnection unit, and exposes the upper surface of the conductive bump; and a second sub-package mounted above the first encapsulant, wherein the second sub-package includes a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on an upper surface of the second substrate, and the second interconnection pattern is electrically coupled with the conductive bump.
According to still another aspect of embodiments of the present application, a modular interconnection unit is provided. The modular interconnection unit may include: a dielectric layer; at least one conductive via passing through the dielectric layer; at least one conductive bump disposed on the dielectric layer and raised from an upper surface of the dielectric layer; and a protection layer disposed on the dielectric layer, wherein the protection layer covers the conductive bump and has a flat upper surface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention. Further, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain principles of the invention.
The drawings referenced herein form a part of the specification. Features shown in the drawing illustrate only some embodiments of the application, and not of all embodiments of the application, unless the detailed description explicitly indicates otherwise, and readers of the specification should not make implications to the contrary.
The same reference numbers will be used throughout the drawings to refer to the same or like parts.
The following detailed description of exemplary embodiments of the application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the application. Those skilled in the art may further utilize other embodiments of the application, and make logical, mechanical, and other changes without departing from the spirit or scope of the application. Readers of the following detailed description should, therefore, not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiment of the application.
In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of “or” means “and/or” unless stated otherwise. Furthermore, the use of the term “including” as well as other forms such as “includes” and “included” is not limiting. In addition, terms such as “element” or “component” encompass both elements and components including one unit, and elements and components that include more than one subunit, unless specifically stated otherwise. Additionally, the section headings used herein are for organizational purposes only, and are not to be construed as limiting the subject matter described.
As used herein, spatially relative terms, such as “beneath”, “below”, “above”, “over”, “on”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “side” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
To address at least one of the above problems, a new modular interconnection unit is provided in the embodiments of the present application. In the modular interconnection unit, a protection layer is formed on an upper surface of the modular interconnection unit to cover the raised conductive bumps. As the protection layer is formed to have a flat upper surface, there would be no vacuum leakage between the vacuum pick-and-place tool and the modular interconnection unit.
Referring to
The modular interconnection unit 200 includes a dielectric layer 210 and at least one conductive via 220 passing through the dielectric layer 210. In some embodiments, the dielectric layer 210 may be a laminate core of a printed wiring board (PWB), and the conductive via 220 may include one or more of Cu, Al, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In some embodiments, the modular interconnection unit 200 may be a semiconductor interposer and can be fabricated using any suitable IC manufacturing processes. For example, the dielectric layer 210 may include silicon and any other semiconductor-based materials, and the conductive via 220 may be formed by filling through-silicon vias (TSVs) with conductive materials.
The modular interconnection unit 200 further includes at least one conductive bump 230 disposed on the dielectric layer 210. The conductive bump 230 may be raised from an upper surface of the dielectric layer 210 and is electrically connected with the conductive via 220. In the example shown in
A protection layer 240 is formed on the dielectric layer 210. The protection layer 240 covers the conductive bump 230 and has a flat upper surface 240a. In some embodiments, the protection layer 240 may include a molding compound or resin, for example, an epoxy-based resin, but the scope of this application is not limited thereto. In some embodiments, a thickness of the protection layer 240 ranges from 105% to 200% (for example, 110%, 130%, 150%, 170% or 190%) of a height of the conductive bump. In some embodiments, a grinding process may be employed to planarize the upper surface 240a of the protection layer 240. As the upper surface 240a of the protection layer 240 is flat, the modular interconnection unit 200 can be easily picked up and placed at a desired location when the vacuum pick-and-place tool 20 applies a suction vacuum pressure on the upper surface 240a of the protection layer 240, as shown in
As shown in
Referring to
Referring to
As the processes of
According to another aspect of the present application, a method for forming a PoP type package is provided. The modular interconnection unit shown in
Referring to
As shown in
Specifically, the first substrate 412 can provide support and connectivity for electronic components and devices mounted thereon. By way of example, the first substrate 412 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnections, or a ceramic substrate. However, the first substrate 412 is not to be limited to these examples. In other examples, the first substrate 412 may include a laminate interposer, a strip interposer, a leadframe, or other suitable substrates. To enhance manufacturing throughput, the first substrate 412 may include a plurality of predefined substrate units arranged in a strip manner, thereby allowing some manufacturing processes to be performed on all the substrate units in parallel. The first substrate 412 also includes a plurality of singulation areas, which can provide respective cutting areas to singulate the substrate units into individual substrate units.
As shown in
In addition, a plurality of first electronic components 415 are mounted on the upper surface 412a of the first substrate 412. The first electronic components 415 can be mounted on the front surface 412a of the first substrate 412 by flip-chip bonding or other suitable surface mounting techniques. For example, solder paste may be deposited or printed onto contact pads where the first electronic components 415 may be surface mounted. Then, the first electronic components 415 may be placed on the upper surface 412a of the first substrate 412 with terminals or contacts of the first electronic components 415 in contact with and over the solder paste. The solder paste may then be reflowed to mechanically and electrically couple the first electronic components 415 to the contact pads on the upper surface 412a of the first substrate 412.
The first electronic components 415 may include any of a variety of types of semiconductor dice, semiconductor packages, or discrete devices. For example, the first electronic components 415 may include an ultra-wideband (UWB) device, a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system on chip (SoC) processor, a sensor, a memory controller, a memory device, an application specific integrated circuit (ASIC), etc.
Referring to
The modular interconnection unit 420 may include a dielectric layer 422, at least one conductive via 424 passing through the dielectric layer 422, and at least one conductive bump 426 disposed on the dielectric layer 422 and raised from an upper surface of the dielectric layer 422. The modular interconnection unit 420 further includes a protection layer 428 covering the conductive bump 426 and having a flat upper surface. The conductive via 424 is electrically coupled with the first interconnection pattern 414 in the first substrate 412. The modular interconnection unit 420 may have a similar structure and configuration as the modular interconnection unit 200 shown in
In some embodiments, solder paste may be deposited or printed onto the first interconnection pattern 414 where the modular interconnection unit 420 may be surface mounted.
Then, a vacuum pick-and-place tool may be used to place the modular interconnection unit 420 to a location above the first interconnection pattern 414 with terminals of the modular interconnection unit 420 in contact with and over the solder paste. The solder paste may be reflowed to mechanically and electrically couple the modular interconnection unit 420 to the contact pads on the first interconnection pattern 414.
Referring to
In some embodiments, the first encapsulant 430 may be formed using a molding process such as a compression molding process or an injection molding process. In some other embodiments, the first encapsulant 430 may be formed using paste printing, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable process. The first encapsulant 430 may be made of a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler, but the scope of this application is not limited thereto.
In some embodiments, a grinding process may be performed on the first encapsulant 430 to planarize the first encapsulant 430 and expose the modular interconnection unit 420.
Referring to
In some embodiments, a laser ablation process may be employed to remove a portion of the protection layer 428 and form a trench 429 in the protection layer 428. The trench 429 exposes at least the upper surface of the conductive bump 426. The laser ablation technique can accurately control a shape and/or a depth of the trench 429. However, the present application is not limited thereto. In other embodiments, the trench 429 may be formed by a dry or wet etching process, or any other process known in the art so long as the material of the protection layer can be removed as desired. In some other embodiments, after forming the trench 429, a cleaning process for removing residuals at the trench may further be performed. It can be appreciated that, when multiple conductive bumps 426 are formed on the modular interconnection unit 420, the laser ablation process may not remove a portion of the protection layer 428 that separates adjacent conductive bumps 426 from each other, to maintain the electrical isolation of these conductive bumps 426. In that case, the laser ablation process may be more like a drilling process to remove the materials above the conductive bumps 426.
Referring to
The second sub-package 440 may include a second substrate 442, a second interconnection pattern 444 formed in the second substrate 442, and at least one second electronic component 445 mounted on an upper surface of the second substrate 442. Further, the second sub-package 440 may include a second encapsulant 448 encapsulating the second electronic component 445. The second electronic components 445 may include any of a variety of types of semiconductor dice, semiconductor packages, or discrete devices. For example, the first electronic components 415 may include a WiFi module, a digital signal processor (DSP), a memory device, a microcontroller, an RF circuit, etc. The second substrate 442 can provide support for the second electronic components 445, and the second interconnection pattern 444 can provide connectivity for the second electronic components 445.
After the second sub-package 440 is mounted on the modular interconnection unit 420, the second interconnection pattern 444 in the second sub-package 440 is electrically connected with the conductive bump 426 of the modular interconnection unit 420, such that the modular interconnection unit 420 can provide connectivity between the first sub-package 410 and the second sub-package 440.
In some embodiments, before the second sub-package 440 is mounted on the modular interconnection unit 420, a solder ball mounting (SBM) process may be performed to form an additional solder ball on the conductive bump 426, such that the solder ball may be raised further than the upper surface of the first encapsulant 430 to ensure contact with the second interconnection pattern 444 of the second sub-package 440.
Afterwards, referring to
The underfill encapsulant 450 may fill in any gaps between the first encapsulant 430 and the second substrate 442 and optionally cover lateral surfaces of the second sub-package 440. The underfill encapsulant 450 may include a polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with or without a filler. In some examples, the underfill encapsulant 450 is formed by depositing a fluid material at a location on the first encapsulant 430 that is next to the second substrate 442, and allowing capillary action to draw the fluid material into the space between the first encapsulant 430 and the second substrate 442.
In the example shown in
Afterwards, referring to
In some embodiments, an electrically conductive bump material is deposited over the first interconnection pattern 414 which is exposed from the lower surface 412b of the first substrate 412 using one of or any combination of the following processes: evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive bump material can be solder, Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
In some embodiments, the bump material may be reflowed by heating the material above its melting point to form the external interconnection balls or bumps 460. In some embodiments, the external interconnection balls or bumps 460 may be compression bonded or thermocompression bonded to the first interconnection pattern 414 exposed from the lower surface 412b. The spherical bumps 460 shown in
Afterwards, as shown in
At last, referring to
The EMI shield 470 may be formed from copper, aluminum, iron, or any other suitable material for EMI shielding. In some embodiments, the EMI shield 470 may be formed by spray coating, plating, sputtering, or any other suitable metal deposition process. The EMI shield 470 may follow the shapes and/or contours of the second sub-package 440 and the lateral surfaces of the first sub-package 410.
Referring to
As shown in
Afterwards, referring to
In some embodiments, an upper portion of the first encapsulant 530 and an upper portion of the protection layer 528 are simultaneously removed by a grinder. The grinding process can also planarize upper surfaces of the first encapsulant 530 and the protection layer 528. In some cases, an upper portion of the conductive bump 526 is also removed in the grinding process to expose more area of the conductive bump 526.
Referring to both
The second sub-package 540 may include a second substrate 542, at least one second interconnection pattern 544 formed in the second substrate 542, and at least one second electronic component 545 mounted on an upper surface of the second substrate 542. Further, the second sub-package 540 may include a second encapsulant 548 encapsulating the second electronic component 545. In some embodiments, solder paste may be deposited or printed onto the conductive bump 526 exposed from the first encapsulant 530 and the protection layer 528. Then, the second sub-package 540 may be placed on the first encapsulant 530 with terminals or contacts of the second sub-package 540 in contact with and over the solder paste. The solder paste may then be reflowed to mechanically and electrically couple the second sub-package 540 to the conductive bump 526.
Afterwards, referring to
According to another aspect of the present application, a semiconductor package is provided.
Referring to
The first sub-package 610 may include a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on an upper surface of the first substrate. The modular interconnection unit 620 may be mounted on the upper surface of the first substrate. The modular interconnection unit 620 may include a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and raised from an upper surface of the dielectric layer, and a protection layer disposed on the dielectric layer and partially covering the conductive bump. The conductive via is electrically coupled with the first interconnection pattern, and an upper surface of the conductive bump is exposed from the protection layer. The first encapsulant 630 is disposed on the upper surface of the first substrate, and the first encapsulant 630 surrounds the first electronic component and the modular interconnection unit 620, and exposes the upper surface of the conductive bump. The second sub-package 640 is mounted above the first encapsulant 630. The second sub-package 640 may include a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on an upper surface of the second substrate, and the second interconnection pattern is electrically coupled with the conductive via. The second sub-package 640 may further include a second encapsulant disposed on the upper surface of the second substrate and encapsulating the second electronic component.
In some embodiments, the semiconductor package 600 may further include an underfill encapsulant 650 between the first encapsulant and the second substrate.
In some embodiments, the semiconductor package 600 may further include a plurality of external interconnection bumps 660 formed on a lower surface of the first substrate. The plurality of external interconnection bumps 660 are electrically coupled with the first interconnection pattern.
In some embodiments, the semiconductor package 600 may further include an EMI shield 670 covering the second sub-package 640 and lateral surfaces of the first sub-package 610.
The semiconductor package 600 can be formed by the steps illustrated in
While the semiconductor package of the present application is described in conjunction with corresponding figures, it will be understood by those skilled in the art that modifications and adaptations to the semiconductor package may be made without departing from the scope of the present invention.
The discussion herein included numerous illustrative figures that showed various portions of a semiconductor package and a method for making the same. For illustrative clarity, such figures did not show all aspects of each example package. Any of the example packages and/or methods provided herein may share any or all characteristics with any or all other devices and/or methods provided herein.
Various embodiments have been described herein with reference to the accompanying drawings. It will, however, be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. Further, other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of one or more embodiments of the invention disclosed herein. It is intended, therefore, that this application and the examples herein be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following listing of exemplary claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310942587.7 | Jul 2023 | CN | national |
