Claims
- 1. A multilayer ceramic device, comprising:
a first ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes; and a second ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes, the second ceramic layer being layered on the first ceramic layer; wherein the first ceramic layer has at least one semiconductor bare chip on a surface of the first ceramic layer that does not face the second ceramic layer, and the semiconductor bare chip includes an electrode part that faces the first ceramic layer surface, and a top part which are coated with a sealing resin, and the second ceramic layer has a land grid array terminal disposed on a surface of the second ceramic layer that does not face the first ceramic layer.
- 2. A multilayer ceramic device as described in claim 1, wherein the first and second ceramic layers each have a different dielectric constant.
- 3. A multilayer ceramic device comprising:
a first ceramic layer having a recess and a multilayer circuit pattern electrically connected through interlayer via holes; a second ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes, the second ceramic layer being layered on the first ceramic layer; at least one semiconductor bare chip mounted on a bottom of the recess defined by the first ceramic layer, wherein the semiconductor bare chip includes an electrode part that faces the bottom of the recess, and a top part of the semiconductor bare chip is coated with a sealing resin; and a land grid array terminal disposed on a surface of the second ceramic layer that does not face the first ceramic layer.
- 4. A multilayer ceramic device as described in claim 1, further comprising:
a third ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes, the third ceramic layer being laminated on a surface of the second ceramic layer that does not face the first ceramic layer; the first ceramic layer having a dielectric constant less than 10, the second ceramic layer having a dielectric constant of 10 or higher, and the third ceramic layer having a dielectric constant less than 10.
- 5. A multilayer ceramic device as described in claim 1, further comprising:
a third ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes, wherein the second ceramic layer is thicker than the first ceramic layer and the third ceramic layer.
- 6. A multilayer ceramic device comprising:
a first ceramic layer having a recess at a top part thereof and a first multilayer circuit pattern electrically connected through interlayer via holes; a second ceramic layer having a second multilayer circuit pattern electrically connected through interlayer via holes, said second ceramic layer being layered on said first ceramic layer; and at least one semiconductor bare chip mounted on a bottom of the recess, wherein the semiconductor bare chip includes an electrode part that faces the recess bottom, and the top of the semiconductor bare chip is coated with a sealing resin.
- 7. A multilayer ceramic device as described in claim 6, wherein the first ceramic layer has an array antenna formed by an electrode pattern disposed on a flat part on a surface of the first ceramic layer that does not face the second ceramic layer.
- 8. A mobile terminal device comprising:
a display; and a communication member having
a multilayer ceramic device comprising:
a first ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes; and a second ceramic layer having a multilayer circuit pattern electrically connected through interlayer via holes, the second ceramic layer being layered on the first ceramic layer; wherein the first ceramic layer has at least one semiconductor bare chip mounted on a surface of the first ceramic layer that does not face the second ceramic layer, the electrode part of the bare chip facing the first ceramic layer surface, and the top part thereof are coated with a sealing resin, and the second ceramic layer has a land grid array terminal disposed on a surface of the second ceramic layer that does not face the first ceramic layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000-192265 |
Jun 2000 |
JP |
|
Parent Case Info
[0001] This is a divisional application of Ser. No. 09/891,296, filed Jun. 27, 2001.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09891296 |
Jun 2001 |
US |
Child |
10370632 |
Feb 2003 |
US |