To obtain the maximum function and efficiency from the minimum package, various types of increased density packages have been developed. Among these various types of packages is the multiple-die semiconductor chip package, commonly referred to as a multi-chip module, multi-chip package or stacked chip package. A multi-chip module includes one or more integrated circuit semiconductor chips, often referred to as circuit die, stacked one onto another to provide the advantages of light weight, high density, and enhanced electrical performance. To stack the semiconductor chips, each chip can be lifted by a chip-bonding tool, which is usually mounted at the end of a pick-and-place device, and mounted onto the substrate or onto a semiconductor chip mounted previously.
In some circumstances, such as when the upper die is smaller than the lower die and the lower die is a peripheral bonded die (that is die with bond pads positioned near the periphery of the die as opposed to a center bonded die in which the bond pads are positioned at a central region of the die), the upper die can be attached directly to the lower die without the use of spacers. However, when spacers are needed between the upper and lower die, spacer die, that is die without circuitry, can be used between the upper and lower die. In addition, adhesives containing spacer elements, typically micro spheres, are often used to properly separate the upper and lower die. See U.S. Pat. Nos. 5,323,060; 6,333,562; 6,340,646; 6,388,313; 6,472,758; 6,569,709; 6,593,662 and U.S. patent Publication No. US 2003/0178710.
After the chip mounting process, bonding pads of the chips are connected to bonding pads of the substrate with Au or Al wires during a wire bonding process to create an array of semiconductor chip devices. Finally, the semiconductor chips and their associated wires connected to the substrate are encapsulated, typically using an epoxy-molding compound, to create an array of encapsulated semiconductor devices. The molding compound protects the semiconductor devices from the external environment, such as physical shock and humidity. After encapsulation, the encapsulated devices are separated, typically by sawing, into individual semiconductor chip packages.
A first aspect of the invention is directed to a multiple-die semiconductor chip package. A first die has a first surface bounded by a periphery and bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery. A second die has an electrically non-conductive second surface positioned opposite the first surface. The first and second die define a first region therebetween. An adhesive/spacer structure, comprising spacer elements within an adhesive, is within the first region. The adhesive/spacer structure contacts the first and second surfaces and adheres the first and second die to one another at a chosen separation. The package may comprise a set of generally parallel wires which define a wire span portion of the first region. The adhesive/spacer structure is preferably located at other than the wire span portion of the first region.
A second aspect of the invention is directed to a method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. An adhesive/spacer material, having spacer elements within an adhesive, is selected. The adhesive/spacer material is deposited onto a first surface of a first die. The first surface is bounded by a periphery and has bond pads. A set of generally parallel wires is bonded to and extends from the bond pads outwardly past the periphery. The set of generally parallel wires define a wire span portion of the first surface. A second die, having an electrically non-conductive second surface, is selected. The second surface of the second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby securing the first and second die to one another at a chosen separation, the wire span portion of the first surface defining a wire span region between the first and second surfaces. The adhesive/spacer material is deposited in a manner to prevent any spacer elements from entering the wire span region.
Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings.
The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGS. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGS.
Several prior art structures and embodiments made according to the invention are discussed below. Like reference numerals refer to like elements.
Spacer elements 50, prior to use, are typically spherical, ellipsoidal, cylindrical with hemispherical or ellipsoidal ends, or the like. After assembly, assuming spacer elements 50 are compressible, spacer elements 50 are compressed to some degree and have flattened areas where they contact upper surface 52 of lower die 42 and the electrically non-conductive lower surface 54 of upper die 44; the shape of such spacers is collectively referred to as generally ellipsoidal. For example, an initially spherical spacer element 50 having an 8 mil (200 micrometer) diameter will typically compress to a height of about 7.5 mil (188 micrometers). The height 56 of spacers 50, which is equal to the distance between surface 52 and 54, is preferably at least equal to loop height 32, is more preferably greater than loop height 32, is even more preferably at least about 10% greater than loop height 32. If desired, the selection of the spacer elements include selecting spacer elements so that height 56 is equal to the design loop height 32 plus an allowance for manufacturing tolerance build-up resulting from making the wire bonds, the variance in the size and compressibility the of spacer elements 50 and other appropriate variables.
Adhesive/spacer material may be deposited using a conventional dispenser capillary. However, it is preferred that the adhesive/spacer material be deposited using a showerhead type of dispenser as shown in the above-mentioned U.S. Provisional Patent Application entitled Adhesive/Spacer Island Structure For Multiple Die Package. Doing so can facilitate the positioning of the adhesive/spacer material at spaced apart locations to provide the desired coverage by adhesive/spacer structure 46. This may be especially advantageous when working with center bonded die.
Spacer elements 50 may also be prevented from incursion into wire span portion 60 by sizing the spacer elements so as not to fit between the generally parallel wires 20. In this way wires 20 act as a sieve or strainer to permit a portion 47 of adhesive 48 to enter into wire span portion 60 but prevent spacer elements 50 from doing so. This is illustrated in
The adhesive/spacer structure according to the invention can be useful for multi-die assembly structures in which the upper die 44 does not extend over the edge of the lower die 42, as illustrated in
Any and all patents, patent applications and printed publications referred to above are incorporated by reference.
Other modification and variation can be made to the disclosed embodiments without departing from the subject of the invention as defined in following claims.
This application claims priority from U.S. Provisional Application No. 60/573,956, filed May 24, 2004, titled “Multiple die package with adhesive/spacer structure and insulated die surface”[; and this application claims priority from related U.S. Provisional Application No. 60/573,903, filed May 24, 2004, titled “Adhesive/spacer island structure for multiple die package”]. This application is related to U.S. application Ser. No. 10/______ Attorney Docket CPAC 1074-2, filed on the same day as this application.
Number | Date | Country | |
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60573956 | May 2004 | US | |
60573903 | May 2004 | US |