This patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2006-37808, filed on Apr. 26, 2006, the contents of which are herein incorporated by reference in their entirety.
1. Technical Field
The present disclosure relates to a semiconductor package structure and, more particularly, to package-on-package (POP) structures.
2. Discussion of Related Art
Semiconductor device fabrication may include a front-end process in which integrated circuit (IC) chips are formed on a wafer through photolithography, deposition, and etching processes, and a back-end process that assembles and packages each of the IC chips. The assembly and packaging role is expanding to include protecting chips from environmental and handling damage, forming lines on chips for transmitting input/output signals, physically supporting chips and providing heat dissipation in chips.
The proliferation of portable electronic devices is pushing semiconductor packaging technology to meet demands for improved electrical capabilities, reduced cost, lighter weight and slimmer profiles. To satisfy these demands, package on package (POP), chip scale packaging (CSP) and wafer-level packaging (WLP) have been introduced.
Referring to
External bumps 40, which are connected to the second external terminals 46, are disposed below the second substrate 20. The external bumps 40 are used as electrical connectors for transmitting electrical signals between the first and second semiconductor chips 15 and 25 and an external electronic device (not shown). The second substrate 20 includes an internal interconnection (not shown) that electrically connects the second internal terminals 44 with the second external terminals 46, and includes middle bumps 30 disposed between the first external terminals 36 and the second internal terminals 44 to provide electrical connection between the first external terminals 36 and the second internal terminals 44.
The first and second semiconductor chips 15 and 25 may have different sizes, whereas the first and second substrates 10 and 20 may have the substantially same size. In the case that a small second semiconductor chip 25 is disposed between the first and second substrates 10 and 20, the first and second substrates 10 and 20 are separated from the perimeter of the second semiconductor chip 25. The middle bumps 30 that are disposed in the spaces between the first and second substrates 10 and 20, provide electrical connection between the first external terminals 36 and the second internal terminals 44. The middle bumps 30 can be at least the height of a space (labeled “h” in
However, it is difficult to reduce the ratio of the size of the middle bumps 30 to the size of the entire package. In the case of package structures having many input/output (I/O) terminals, the size of the middle bumps 30 can result in an increase in the total size of the package.
Part-related warpage may occur in connecting the first package and the second package, which are prepared by different processes. The first and second packages may deform differently under subsequent processes due to various factors such as thermal stress, and this difference in deformation between the first and second packages results in warpage. However, conventional methods are insufficient to avoid warpage in structures in which the first and second packages are connected by using the middle bumps 30.
In an exemplary embodiment of the present invention, a package-on-package (POP) structure includes a first semiconductor chip disposed on a first substrate including a plurality of first internal terminals and a plurality of first external terminals; a second semiconductor chip disposed on a second substrate including a plurality of second internal terminals and a plurality of second external terminals and a connecting structure electrically connecting at least one of the first external terminals to at least one of the second external terminals.
In an exemplary embodiment of the present invention, a POP structure includes a first bonding member connecting the first semiconductor chip to the first internal terminals of the first substrate, and a second bonding member connecting the second semiconductor chip to the second internal terminals of the second substrate. The first and the second bonding members may be a wire bonding structure or a solder bump structure. The connecting structure may include wires directly connecting the first external terminals to the second external terminals, and a protective layer pattern disposed between the first substrate and the second substrate and encapsulating the wires.
The first substrate may include a first interconnection structure electrically connecting the first internal terminals with the first external terminals, and the second substrate may include a second interconnection structure electrically connecting the second internal terminals with the second external terminals.
In an exemplary embodiment of the present invention, a POP structure may include external bump pads coupled to at least one of the first external terminals that is not connected to the connecting structure, and internal bump pads coupled to at least one of the second external terminals that is not connected to the connecting structure. The external bump pads may have a thickness of about 80% to about 120% of a thickness of the internal bump pads.
The first interconnection structure may include at least one first internal interconnection connecting the first internal terminals to the external bump pads, second internal interconnections connecting at least one of the first external terminals that is connected to the connecting structure to at least one of the first external terminals that is not connected to the connecting structure, and third internal interconnections connecting at least one of the first external terminals that is connected to the connecting structure to the first internal terminals and at least one of the first external terminals that is not connected to the connecting structure.
The second interconnection structure may include at least one fourth internal interconnection connecting the second internal terminals to the internal bump pads, fifth internal interconnections connecting at least one of the second external terminals that is connected to the connecting structure to at least one of the second external terminals that is not connected to the connecting structure, and sixth internal interconnections connecting at least one of the second external terminals that is connected to the connecting structure to the second internal terminals and to at least one of the second external terminals that is not connected to the connecting structure.
In an exemplary embodiment of the present invention, a POP structure may include internal bump pads coupled to at least one of the second external terminals that is not connected to the connecting structure, wherein the first external terminals may all be connected to at least one of the second external terminals through the connecting structure.
The first substrate may have a greater surface area than the second substrate, and the first substrate may include a concaved lower surface with a circumvallation part defining a predetermined recessed region. The second substrate may be coupled to the recessed region of the first substrate through an adhering member. The circumvallation part may have a thickness of about 50% to about 100% of a distance between a lower surface of the second substrate and a lower surface of the recessed region.
In an exemplary embodiment of the present invention, a POP structure may include at least one middle substrate disposed between the first substrate and the second substrate, and including middle internal terminals and middle external terminals, and a middle semiconductor chip coupled to the middle substrate, wherein at least one of the middle external terminals may be electrically connected to at least one of the first external terminals and the second external terminals.
The present invention will become readily apparent to those of ordinary skill in the art when descriptions of exemplary embodiments thereof are read with reference to the accompanying drawings.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the sizes and thicknesses of layers and regions may be exaggerated for clarity.
Referring to
An upper region of the first substrate 110 includes first internal terminals 134 disposed thereon, and a lower region includes first external terminals 136 disposed thereon, as shown in
As shown in
According to an exemplary embodiment of the present invention, the lower surface of the first substrate 110 includes a circumvallation part 114 formed thereon that defines a recessed region 112, wherein the first substrate 110 is thinner at the recessed region 112 than at the circumvallation part 114. For example, the first substrate 110 is formed as a concaved structure. The second package may use a member (not shown) to attach to the bottom surface of the recessed region 112. To reduce the discrepancy in the height between the first substrate 110 and the second substrate 120, the circumvallation part 114 may have a thickness that is about 50% to about 100% of that of the second package. According to an exemplary embodiment of the present invention, the substrate height reduction due to the circumvallation part eliminates the need for a middle bump, and warpage may be avoided and an increase in size of the overall package can be prevented.
The first substrate 110 may include a first interconnection structure for connecting the first internal terminals 134 to the first external terminals 136, and the second substrate 120 may include a second interconnection structure for connecting the second internal terminals 144 to the second external terminals 146. The first external terminals 136 may use a connecting structure 200 to directly connect to the second external terminals 146. The connecting structure 200 may include wires 201 connecting the first external terminals 136 to the corresponding second external terminals 146 and may include a protective layer pattern 202 encapsulating the wires 201. The wires 201 may be formed using conventional wire bonding techniques. The protective layer pattern 202 may be disposed between the first substrate 110 and the second substrate 120, for example, to protect the wires 201 from physical and chemical damage. The protective layer pattern 202 may be formed of an epoxy material and may fill the recessed region 112 in which the second package is disposed.
In an exemplary embodiment of the present invention, the first substrate 110 and the second substrate 120 are electrically connected through the wires 201, and the first and second packages can be protected from warpage even when the positions of the lower surfaces of the first substrate 110 and the second substrate 120 are different, and the bonding process may not be restricted due to the wires 201.
In an exemplary embodiment of the present invention, all of the first external terminals 136 are connected to the connecting structure 200, and the connecting structure 200 is connected to a set of the second external terminals 146. The internal bumps 140 shown in
In an exemplary embodiment of the present invention, the internal bumps 140 are electrically connected to the first and second semiconductor chips 115 and 125 through the first and second interconnections and the connecting structure 200. For example, all of the first internal terminals 134 may be electrically connected to the first external terminals 136 through the first interconnection structure, and the second internal terminals 144 may be electrically connected to the second external terminals 146 through the second interconnection structure. When all of the first external terminals 136 are electrically connected to the second external terminals 146 through the connecting structure 200, all of the first internal terminals 134 may also be electrically connected to the second external terminals 146.
In an exemplary embodiment of the present invention, at least one of the second internal terminals 144 is connected to the connecting structure 200 (as shown in dashed block 301 of
It is to be understood that the first interconnection structure may be formed differently than that shown in
A package structure according to an exemplary embodiment of the present invention uses the connecting structure 200 and the second interconnection structure to connect the first and second semiconductor chips 115 and 125 to the internal bumps 140, such that the number of bumps for connecting to an external electronic device may be reduced. As shown by dashed block 301 in
Referring to
The first interconnection structure may each include a first internal interconnection connected to the external bumps 150, a second internal interconnection connected to the connecting structure 200, and a third internal interconnection commonly connected to the external bumps 150 and the connecting structure 200. The second interconnection structure may include a structure with fourth through sixth internal interconnections that correspond to the first through third internal interconnections of the first interconnection structure. In an exemplary embodiment of the present invention, the third through sixth internal interconnections have a connecting structure, such as that shown in dashed block 301 of
According to an exemplary embodiment of the present invention, the connecting structure including the wires 201 connects the first and second packages, and warpage may be avoided. When the first substrate 110 includes the circumvallation part 114, according to an exemplary embodiment of the present invention, the middle bumps can be eliminated and warpage may be avoided and increased overall package size may be prevented.
Referring to
Referring to
As shown in
For providing a secure connection with an external electronic device, the lower surfaces of the external bumps 150 and the internal bumps 140 may be even, as shown
Referring to
As shown in
At least one middle package may be disposed between the first package and the second package. The middle package may electrically connect the first and second packages. For example, this electrical connection may be formed similar to the substrate and interconnection structures described in connection with
The plurality of manufactured semiconductor chips may be packaged using a flip-chip method. In a flip-chip method, bumps for connecting to an external electronic device are formed on the top of a semiconductor chip itself. A package structure employing a flip-chip method according to an exemplary embodiment of the present invention will be described with reference to
Referring to
At least one of the first input/output terminals 116 of the first semiconductor chip 115 is electrically connected to the second external terminals 146 of the second package through the connecting structure 200. The connecting structure 200 and the second package of
Referring to
A portion of the second input/output terminals 126 of the second semiconductor chip 125 is electrically connected to the first external terminals 136 of the first package through the connecting structure 200. The connecting structure 200 and the first package of
Referring to
At least one of the second input/output terminals 126 of the second semiconductor chip 125 is electrically connected to at least one corresponding one of the first input/output terminals 116 of the first semiconductor chip 115 through the connecting structure 200. The connecting structure 200 of
The first and second packages according to exemplary embodiments of the present invention are electrically connected through wires such that they become packages that are not prone to warpage and may require a lesser number of bumps for connecting to an external electronic device.
According to exemplary embodiments of the present invention, a circumvallation part is disposed on the bottom surface of the first substrate to reduce the discrepancy in the height between the lower surfaces of the first and second substrates and separate bumps are not required between the first and second substrates, and warpage may be avoided and an overall size increase of the package can be prevented.
Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings for the purpose of illustration, it is to be understood that inventive processes and apparatus should not be construed as limited thereby. It will be readily apparent to those of ordinary skill in the art that various modifications to the foregoing exemplary embodiments can be made without departing from the scope of the present invention as defined by the appended claims, with equivalents of the claims to be included therein.
Number | Date | Country | Kind |
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2006-37808 | Apr 2006 | KR | national |