The disclosure generally relates to a package structure and a manufacturing method thereof, and in particular, to a package structure having a bridge die and a manufacturing method thereof.
In the development of semiconductor package technology, a focus is to produce package structures with higher densities of components and interconnects, and ever higher performances, while maintaining or increasing a high reliability and durability at a lower manufacturing cost. One strategy is to employ bridge dies as interconnects for other dies within the package structure. One of the challenges lies in how to connect the bridge die with the other dies, such that a high broadband transfer of signals may be achieved between the dies in a reliable, durable and cost-effective package structure.
The disclosure provides a package structure and a manufacturing method thereof, which provides for a higher density of interconnecting routes between dies therein in a reliable, durable package structure that can be manufactured at a lower cost.
The disclosure provides a package structure including a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die is disposed on the redistribution structure. The conductive pillars are disposed at a periphery of the bridge die and on the redistribution structure, and are electrically connected to the redistribution structure. The at least two dies are disposed on the bridge die and the conductive pillars opposite to the redistribution structure. Each of the at least two dies has an active surface and a lateral surface connected to the active surface and includes a plurality of conductive pads disposed on the active surface and electrically connected to the bridge die and the conductive pillars. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers the active surface and the lateral surface of each of the at least two dies.
The disclosure provides a manufacturing method of a package structure. The method includes at least the following steps. A carrier is provided. At least two dies are disposed on the carrier. Each of the at least two dies has an active surface and a rear surface opposite the active surface and includes a plurality of conductive pads disposed on the active surface. The rear surface faces the carrier. A bridge die is disposed and a plurality of conductive pillars is formed on the at least two dies opposite to the carrier. The bridge die has an active surface and a rear surface opposite the active surface of the bridge die. The bridge die is electrically connected to each of the at least two dies through the active surface of the bridge die. The conductive pillars are electrically connected to each of the at least two dies. An insulating encapsulant is formed to encapsulate the at least two dies, the bridge die and the conductive pillars. A redistribution structure is formed on the insulating encapsulant opposite to the carrier. The redistribution structure is electrically connected to the conductive pillars. The carrier is removed from the insulating encapsulant and the at least two dies.
Based on the above, the bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies. The higher density of interconnecting routes allows for a high bandwidth transfer of signals between the at least two dies. The high bandwidth allows for faster communication between, for example, processor and memory dies, and thereby a faster operation of the package structure. The insulating encapsulant provides additional mechanical support to the electrical connection from the redistribution structure to the at least two dies, that is the conductive pillars electrically connecting the at least two dies to the redistribution structure. The additional mechanical support increases a reliability and durability of the package structure at a lower manufacturing cost.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles presented in the disclosure. Identical or similar numbers refer to identical or similar elements throughout the drawings.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Referring to
Each of the at least two dies includes a semiconductor substrate and a plurality of conductive pads. The conductive pads include a plurality of first conductive pads and a plurality of second conductive pads. The first die 110 may include a semiconductor substrate 111 and a plurality of conductive pads 112. The second die 120 may include a semiconductor substrate 121 and a plurality of conductive pads 122. The conductive pads 112 include a plurality of first conductive pads 112a and a plurality of second conductive pads 112b. The conductive pads 122 include a plurality of first conductive pads 122a and a plurality of second conductive pads 122b.
In some embodiments, the semiconductor substrate 111 and the semiconductor substrate 121 may be a silicon substrate including active components (e.g., transistors or the like) and, optionally, passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. The conductive pads 112 are distributed on the semiconductor substrate 111 on the active surface 110a. The conductive pads 122 are distributed on the semiconductor substrate 121 on the active surface 120a. The conductive pads 112 and 122 may include aluminum pads, copper pads, or other suitable metal pads.
Referring to
After forming the first insulating encapsulant 150, a passivation layer 152 may be formed on the first insulating encapsulant 150 and the at least two dies. The passivation layer 152 may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed of polymeric materials or other suitable dielectric materials. A plurality of openings is formed in the passivation layer 152 to expose at least a portion of each of the conductive pads of each of the at least two dies.
Referring to
As illustrated in
The bridge die 130 may be a passive die, wherein the semiconductor substrate 131 includes conductive traces and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein such that electrical signals may be transmitted between the first die 110 and the second die 120. Alternatively, the bridge die 130 may be an active die, wherein the semiconductor substrate 131 includes active components (e.g., transistors or the like) in addition to the conductive traces and optionally the passive components. The bridge die 131 may be a digital die, analog die, or mixed signal die. For example, the bridge die may be an application-specific integrated circuit (ASIC) die, logic die, or other suitable die.
In some embodiments, an underfill 180 is formed between the passivation layer 152 and the bridge die 130 to protect and isolate the electrical connection between the conductive bumps 132 and the first conductive vias 160a. The underfill 180 may be formed by a capillary underfill (CUF) process and may include polymeric materials, resins, or silica additives.
The conductive pillars 170 may be formed on the passivation layer 152, wherein each conductive pillars 170 is directly in contact with one of the second conductive vias 160b. The conductive pillars 170 may be formed using lithography, plating, photoresist stripping, or any other suitable processes. The conductive pillars 170 may be made of copper, aluminum, nickel, gold, a combination thereof, or other suitable conductive materials. The conductive pillars 170 may be formed by forming a mask (not shown) having openings, where the openings expose a portion of the passivation layer 152; disposing a conductive material to fill the openings of the mask by plating or deposition; and removing the mask to form the conductive pillars 170. The conductive pillars 170 may be formed such that top surfaces 170t of the conductive pillars 170 and the rear surface 130b of the bridge die 130 are colinear. However, the present disclosure is not limited thereto, for instance, the conductive pillars 170 may be formed such that the top surfaces 170t are higher than the rear surface 130b of the bridge die 130. A width 170w of each of the conductive pillars 170 may be greater than a width 160bw of the second conductive vias 160b, but the present disclosure is not limited thereto.
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In the exemplary embodiment of
In some embodiments, the bottom portion of the conductive traces may also be in direct contact with the rear surface 130b of the bridge die 130. A conductive trace of the conductive traces of the redistribution structure 192 may electrically connect with a conductive trace of the conductive traces of the semiconductor substrate 131 of the bridge die 130. In some embodiments, the semiconductor substrate 131 may include through silicon vias (TSV) to electrically connect a conductive trace of the redistribution structure 192 to one or more of the at least two dies, for instance the first die 110 or the second die 120, directly through the bridge die 130.
A top dielectric layer of the redistribution structure 192 is on the opposite side of the redistribution structure 192 to the bottom dielectric layer and exposes a top portion of the conductive traces. The top portion of the conductive traces may be formed as a plurality of under-ball metallization (UBM) pads. A plurality of conductive terminals 194 may be formed on the top portion of the conductive traces of the redistribution structure 192. The conductive terminals 194 may be formed by a ball placement process and/or a reflow process. The conductive terminals 194 may be conductive bumps such as solder balls. However, the present disclosure is not limited thereto. In some alternative embodiments, the conductive terminals 194 may take other possible forms and shapes based on design requirements. For example, the conductive terminals 194 may take the form of conductive pillars or conductive posts.
The redistribution structure 192 may be used to reroute electrical signals to/from the first die 110 and the second die 120, and may expand to a wider area than that of the at least two dies. Therefore, in some embodiments, the redistribution structure 192 may be referred to as a “fan-out redistribution structure”. As well as electrically connecting onward to other package structures or devices through the conductive terminals 192, the redistribution structure 192 may also electrically connect any conductive component of the package structure 100 to each other, if that conductive component is electrically connected to the redistribution structure 192. For example, the first die 110 and the second die 120 may also be electrically connected through the redistribution structure 192.
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By using the bridge die 130 having the conductive bumps 132a and 132b, which can also be referred to as conductive microbumps, having a width and spacing of less than 2 micrometers to route signals between the first die 110 and the second die 120, a high density of interconnecting routes may be provided. The higher density of interconnecting routes allows for a high bandwidth transfer of signals between the first die 110 and the second die 120. The high bandwidth allows for faster communication between, for example, processor and memory dies, and thereby a faster operation of the package structure 100. Furthermore, the passivation layer 152, as well as isolating the first die 110 and the second die 120 from the bridge die 130, also provides a suitable surface to which the underfill 180 of the bridge die 130 can adhere to. The passivation layer 152 and underfill 180 of the bridge die 130 provide additional mechanical support to the interconnect assembly between the bridge die 130 and the at least two dies, that is the conductive bumps 132 of the bridge die 130 and the first conductive vias 160a. The passivation layer 152 also provides additional mechanical support to the interconnect assembly between the at least two dies and the redistribution structure 192, that is the conductive pillars 170 and the second conductive vias 160b. The additional mechanical support increases a reliability and durability of the package structure 100.
In some embodiments, having the bridge die 130 directly adjacent to the redistribution structure 192, allows for a direct electrical connection between the redistribution structure 192 and the bridge die 130 through the rear surface 130b of the bridge die 130, and also allows for an electrical connection from the redistribution structure 192 to the first die 110 or the second die 120 through, for example, a through silicon via (TSV) in the bridge die 130.
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A thickness of the insulating material 253 and the conductive connector 240 is reduced to expose the top surfaces 270t of the conductive pillars 270 and the rear surface 230b of the bridge die 230, thereby forming the second insulating encapsulant 254. In some embodiments, the top surfaces 270t, the rear surface 130b and a top surface 240t of the conductive connector 240 are substantially coplanar to each other. The second insulating encapsulant 254 may be formed and made of a material as described for the second insulating encapsulant 154 of the package structure 100.
Referring to
After forming the redistribution structure 292, the manufacturing method of the package structure 200 follows the above described manufacturing method of the package structure 100 as shown in
In some embodiments, the package structure 300 may include a chip stack, a redistribution layer electrically connected to the chip stack, an insulator disposed on the redistribution layer to encapsulate the chip stack, and external terminals electrically connected to the redistribution layer and opposite to the chip stack. The chip stack may be electrically connected to the redistribution layer through a plurality of conductive wires, but the present disclosure is not limited thereto. The insulator may encapsulate the conductive wires. The chip stack may comprise of a plurality of chips stacked on each other. The chips may include memory chips having non-volatile memory, such as NAND flash. However, the present disclosure is not limited thereto. In some alternative embodiments, the chips of the chip stack may include chips capable of performing other functions, such as logic functions, computing functions, or the like. A chip attachment layer may be disposed between two adjacent chips in the chip stack to enhance an adhesion between the two adjacent chips. It should be noted that the number of the chips shown to be stacked in the chip stack in
After disposing the package structure 300 on the package structure 200, the external terminals of the package structure 300 may be positioned on the conductive connectors 240 of the package structure 200. A reflow process may be performed to bond the external terminals of the package structure 300 to the conductive connectors 240. Alternatively, other suitable methods may be used to attach the package structure 300 onto the package structure 200 to form the PoP structure 400.
As such, the package structure may include the conductive connectors, for example fanout through insulator vias (FO-TIV), to connect to another package structure stacked on top, thereby forming a PoP structure.
Based on the above, the bridge die of the package structure may be used to route signals between the at least two dies. The bridge die has conductive bumps, which can also be referred to as conductive microbumps, having a width and spacing of less than 2 micrometers that allow for a higher density of interconnecting routes between the at least two dies. The higher density of interconnecting routes allows for a high bandwidth transfer of signals between the at least two dies. The high bandwidth allows for faster communication between, for example, processor and memory dies, and thereby a faster operation of the package structure. Furthermore, the passivation layer, as well as isolating the at least two dies from the bridge die, also provides a suitable surface to which the underfill of the bridge die can adhere to. The passivation layer and underfill of the bridge die provide additional mechanical support to the interconnections within the package structure, thereby increasing the reliability and durability of the package structure.
Additionally, the bridge die may be disposed directly adjacent to the redistribution structure, allowing for a direct electrical connection between the redistribution structure and the bridge die through the rear surface of the bridge die. Such an arrangement also permits the addition of an electrical connection from the redistribution structure to one or more of the at least two dies through, for example, through silicon vias (TSV) in the bridge die.
The manufacturing method of the package structure does not require an expensive boring process in order to form the conductive pillars connecting the at least two dies to the redistribution structure, thereby reducing the time and cost of the manufacturing process of the package structure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments and concepts disclosed herein without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.