Claims
- 1. A multichip module packaging structure comprising:
- a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;
- at least one integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads in an optically observable alignment, said I/O connection pads thermosonically bonded to said first bonding pads to register said at least one integrated circuit die with said thin film multilayer interconnect circuit.
- 2. A multichip module packaging structure comprising:
- a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;
- at least one integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said I/O connection pads thermosonically bonded to said first bonding pads to register said at least one integrated circuit die with said thin film multilayer interconnect circuit; and a layer of encapsulant disposed over said second surface of said at least one integrated circuit die in said at least one chip mounting cavity, said layer of encapsulant forming a passivation layer over said integrated circuit die, and wherein a portion of said encapsulant disposed between said first surface of said at least one integrated circuit die and said first surface of said thin film multilayer interconnect circuit.
- 3. A multichip module packaging structure comprising:
- a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavities formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;
- a plurality of integrated circuit die having first and second surfaces, one of said integrated circuit die disposed entirely within said plurality of chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads in an optically observable alignment, said I/O connection pads thermosonically bonded to said first bonding pads to register each of said integrated circuit die with said thin film multilayer interconnect circuit.
- 4. A multichip module packaging structure comprising:
- a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavities formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;
- a plurality of integrated circuit die having first and second surfaces, one of said integrated circuit die disposed entirely within said plurality of chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said I/O connection pads thermosonically bonded to said first bonding pads to register each of said integrated circuit die with said thin film multilayer interconnect circuit; and a layer of encapsulant disposed over said second surfaces of said plurality of integrated circuit die in said at least one chip mounting cavity, said layer of encapsulant forming a passivation layer over said integrated circuit die, and wherein a portion of said encapsulant is disposed between said first surfaces of said plurality of integrated circuit die and said first surface of said thin film multilayer interconnect circuit.
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of patent application Ser. No. 08/060,406, filed May 11, 1993, now U.S. Pat. No. 5,422,514.
US Referenced Citations (8)
Continuations (1)
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Number |
Date |
Country |
Parent |
060406 |
May 1993 |
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