BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a conventional plate structure having a chip embedded therein;
FIGS. 2
a to 2g are cross-sectional views of the manufacturing method of the plate structure in one embodiment of the present invention.
FIGS. 3
a to 3c are cross-sectional views of the manufacturing method of the build-up structure in one embodiment of the present invention.
FIG. 4 is a cross-sectional view of the manufacturing method in another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Embodiment 1
With reference to FIGS. 2a to 2g, there is shown a cross-sectional view of the manufacturing method of the plate structure having a chip in one embodiment of the present invention.
As shown in FIG. 2a, an aluminum plate 10 is first provided. Subsequently, a first patterned resistive layer 11, which is required to be adhered to the surface of the aluminum plate 10, is formed as shown in FIG. 2b.
The aluminum plate 10 is put into an electrolytic tank to perform oxidization. The part of the aluminum plate 10 not covered by the first patterned resistive layer 11 is gradually oxidized to become aluminum oxide 12 having an insulating property, but the other part of the aluminum plate 10 covered by the first patterned resistive layer 11 is still aluminum 13 having a conductive property (the structure thereof as shown in FIG. 2c). Because the aluminum part of the aluminum oxide plate 14 has to conduct to the first and the second surfaces of the aluminum oxide plate 14, an aluminum channel 15 with a conductive property is formed inside the aluminum oxide plate 14. In the present embodiment, the aluminum plate 10 with the first patterned resistive layer 11 adhered thereon is put into an electrolytic tank filled with a solution of oxalic acid or sulfuric acid to perform anodic oxidation. Through controlling the duration of anodic oxidation, and the width or the shape of the first patterned resistive layer 11, the width of the aluminum channel 15 inside the aluminum oxide layer 14 is determined.
Thus, in the present embodiment, it can be seen that the aluminum oxide plate (insulator) and the aluminum channels (conductor) therein are simultaneously completed. In other words, in the present embodiment, the insulator plate and the conductive channels between the top and the second surface of the insulator plate are formed at one time without additional steps being necessary to manufacture circuits conducting to electronic devices.
Subsequently, as shown in FIG. 2d, the first patterned resistive layer 11 on the aluminum oxide plate 14 is removed to expose the two terminals of the aluminum channel 15. Conductive pads 17 are formed on the both exposed terminals of the aluminum channel 15, as shown in FIG. 2e. The formation method of the conductive pads 17 is first to form a patterned resistive layer (not shown in figures) on the top and the second surface of the aluminum oxide plate 14. Then, after a copper layer is plated or deposited on the part not covered by the above patterned resistive layer, the above patterned resistive layer is removed. Consequently, the conductive pads 17 are completed. Because the formation method of the conductive pad 17 is conventional it is not shown in the figures. After aforementioned steps are completed, a cavity 16 is formed by a router cutting the aluminum oxide plate 14. A chip 21, which is completed by a wafer integrated circuit process and die sawing, is embedded into the cavity 16 of the aluminum oxide plate 14, and has plural electrode pads 23 made of copper attached on an active surface 22 thereof. Subsequently, the epoxy resin 25 is filled into gaps between the aluminum oxide plate 14 and the chip 21 to secure the chip 21 in the cavity 16 of the aluminum oxide plate 14, as per the structure shown in FIG. 2f. In the present embodiment, the exposed back surface 24 of the chip 21 is advantageous in providing a good heat-dissipating surface.
After completing the aforesaid steps, at least one build-up structure 31 is formed on the surface of the aluminum oxide plate 14 and the active surface of the chip 21, as per the structure shown in FIG. 2g. The formation method of the build-up structure 31 is shown from FIG. 3a to FIG. 3c. First, a dielectric layer 32 is formed on the surface of the aluminum oxide plate 14 and the active surface 22 of the chip 21. The material of the dielectric layer 32 is selected from any one of a group consisting of Ajinomoto Build-up Film (ABF), bismaleimide triazine (BT), benzocyclobutene (BCB), liquid crystal polymer, polyimide (PI), poly(phenylene ether), aramide, epoxy resin, poly(tetra-fluoroethylene), and fiber glass. Plural vias 33 are formed on the dielectric layer 32 through laser ablation, or exposing and developing, and at least one corresponds to the electrode pad 23 of the chip 21, as per the structure shown in FIG. 3a. If utilizing laser ablation, a de-smearing step is then performed to remove any possible residual smear due to ablation in the via of the dielectric layer. Then, a seed layer 40 is formed on the dielectric layer 32 and in the via 33 of the dielectric layer. Further, a resistive layer 34 is formed on the surface of the seed layer 40. Subsequently, plural openings 35 are formed through exposing and developing the resistive layer 34, and at least one corresponds to the electrode pad 23 of the chip 21. Finally, as shown in FIG. 3c, electroplating metal layers 36 are plated in the plural openings 35 of the resistive layer. The resistive layer 34 and the seed layer 40 covered by the electroplating metal layers 36 are removed. The build-up structure 31 shown in FIG. 2g is a multilayer structure, and is stacked up by way of build-up technology. The electroplating metal layer 36 includes a circuit layer 37 and a conductive structure 38 conducting to the electrode pad 23 of the chip 21.
As shown in FIG. 2g, a solder mask layer 50 as an insulating protection layer is formed on the surface of the build-up structure 31. Plural openings 51 are formed on the solder mask layer 50 to expose the conductive pads 31a on the surface of the build-up structure 31. Plural solder bumps 41 are disposed in the openings 51 of the solder mask layer 50, and conduct to the build-up structure 31. Electronic devices 42 are disposed on the surface of the conductive pads 17 on the aluminum oxide plate 14 to conduct to the aluminum channels 15. Thus, the plate structure having a chip embedded therein in the present embodiment is completed.
Accordingly, when integrating the electronic devices 42 on the aluminum oxide plate 14 of the present embodiment, the aluminum channel 15 can be a circuit conducting to the top and bottom surface of the aluminum oxide plate 14, and consequently the electronic devices 42 are conductive.
Embodiment 2
The method for manufacturing a plate having a chip embedded therein of the present embodiment is very similar to the embodiment 1. Except for the step of securing the chip and the aluminum material being different from embodiment 1, everything else is approximately the same as in embodiment 1.
As shown in FIG. 4, after the chip 21 is embedded into the cavity of the aluminum oxide plate 14, a dielectric material layer 26 is coated on the surface of the aluminum oxide plate 14, and filled between the chip 21 and the aluminum oxide plate 14 through laminating to secure the chip 21 in the cavity of the aluminum oxide plate 14. The dielectric material layer 26 on the second surface of the aluminum oxide plate 14 can be seen as one of the dielectric layers of the build-up structure. Then, the steps of forming the build-up structure are continued. Finally, plural solder bumps are formed on the build-up structure, and the electronic devices are integrated. The plate structure having a chip embedded therein of the present embodiment is completed.
Similarly, when electronic devices of the aluminum oxide plate 14 in the present embodiment are integrated, the aluminum channel 15 can be a conductive circuit between the top and bottom of the aluminum oxide plate 14 to conduct to the electronic devices.
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the scope of the invention as hereinafter claimed.
Patent Application
20080029872
