Claims
- 1. A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component, the process comprising the steps of:
oxidizing at least a portion of the at least one thin-film layer; etching the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.
- 2. A process as claimed in claim 1 wherein the oxidizing and etching steps are executed in a generally concurrent manner.
- 3. A process as claimed in claim 1 wherein the oxidizing and etching steps are executed in a sequential manner and the etching step is executed in a generally non-oxidizing atmosphere.
- 4. A process as claimed in claim 1 wherein the etching step is executed in a generally non-oxidizing atmosphere.
- 5. A process as claimed in claim 1 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising sulfuric acid.
- 6. A process as claimed in claim 1 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising sulfuiric acid, hydrochloric acid, and water.
- 7. A process as claimed in claim 1 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising 1-5% sulfuric acid by volume, 0.1-0.5% hydrochloric acid by volume, and water.
- 8. A process as claimed in claim 1 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising water, sulfamic acid, and iron (III) chloride.
- 9. A process as claimed in claim 8 wherein the etchant further comprises a weak acid selected from the group consisting of acetic acid, butyric acid, formic acid, and propionic acid.
- 10. A process as claimed in claim 8 wherein the etchant further comprises a surfactant.
- 11. A process as claimed in claim 8 wherein the etchant further comprises diethylene glycol butyl ether.
- 12. A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component, the process comprising the steps of:
providing a protective mask having a pattern over the at least one thin-film layer; oxidizing portions of the at least one thin-film layer that are exposed by the protective mask; etching the oxidized thin-film layer using an etchant that selectively etches the oxidized portions of the at least thin-film layer without substantial etching of regions of the at least one thin-film layer covered by the protective mask.
- 13. A process as claimed in claim 12 wherein the oxidizing and etching steps are executed in a generally concurrent manner.
- 14. A process as claimed in claim 12 wherein the oxidizing and etching steps are executed in a sequential manner and the etching step is executed in a generally non-oxidizing atmosphere.
- 15. A process as claimed in claim 12 wherein the etching step is executed in a generally non-oxidizing atmosphere.
- 16. A process as claimed in claim 12 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising sulfuric acid.
- 17. A process as claimed in claim 12 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising water, sulfamic acid, and iron (III) chloride.
- 18. A process as claimed in claim 12 wherein the etchant further comprises a weak acid selected from the group consisting of acetic acid, buteric acid, formic acid, and propionic acid.
- 19. A process as claimed in claim 17 wherein the etchant further comprises a suffactant.
- 20. A process as claimed in claim 17 wherein the etchant further comprises diethylene glycol butyl ether.
- 21. A process as claimed in claim 12 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising sulfuric acid, hydrochloric acid, and water.
- 22. A process for manufacturing a microelectronic interconnect or component formed of copper on a surface of a workpiece, the process comprising the steps of:
depositing a copper seed layer over a surface of the workpiece using a physical vapor deposition process; electrochemically depositing one or more copper structures over the copper seed layer through one or more patterned openings formed in at least one patterned mask overlying the seed layer; removing the at least one patterned mask; etching the seed layer and the one or more copper structures using an etchant that etches the seed layer at and equal or greater rate than the etching rate of the one or more copper structures.
- 23. A process as claimed in claim 22 wherein the etching step comprises the steps of:
oxidizing the seed layer and the one or more copper structures; etching the oxidized the seed layer and the one or more copper structures using an etchant that selectively etches primarily the oxidized portions of the seed layer and the one or more copper structures.
- 24. A process as claimed in claim 23 wherein the oxidizing and etching steps are executed in a generally concurrent manner.
- 25. A process as claimed in claim 23 wherein the oxidizing and etching steps are executed in a sequential manner and the etching step is executed in a generally non-oxidizing atmosphere.
- 26. A process as claimed in claim 23 wherein the etching step is executed in a generally non-oxidizing atmosphere.
- 27. A process as claimed in claim 23 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising suifuric acid.
- 28. A process as claimed in claim 23 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising water, sulfamic acid, and iron (III) chloride.
- 29. A process as claimed in claim 28 wherein the etchant further comprises a weak acid selected from the group consisting of acetic acid, buteric acid, formic acid, and propionic acid.
- 30. A process as claimed in claim 28 wherein the etchant further comprises a surfactant.
- 31. A process as claimed in claim 28 wherein the etchant further comprises diethylene glycol butyl ether.
- 32. A process for manufacturing a microelectronic interconnect or component formed of copper on a surface of a workpiece, the process comprising the steps of:
depositing a copper seed layer over a surface of the workpiece;, electrochemically depositing a patterned copper layer over the copper seed layer; exposing the copper seed layer and the patterned copper layer to an etchant for a predetermined period of time, the predetermined period of time being selected to allow substantial removal of the copper seed layer by the etchant while preventing substantial removal of the electrochemically deposited patterned copper layer by the etchant.
- 33. A process as claimed in claim 32 wherein the exposing step comprises the steps of:
oxidizing the seed layer and the deposited copper layer; etching the oxidized the seed layer and the deposited copper layer using an etchant that selectively etches primarily the oxidized portions of the seed layer and the deposited copper layer.
- 34. A process as claimed in claim 33 wherein the oxidizing and etching steps are executed in a generally concurrent manner.
- 35. A process as claimed in claim 33 wherein the oxidizing and etching steps are executed in a sequential manner and the etching step is executed in a generally non-oxidizing atmosphere.
- 36. A process as claimed in claim 32 wherein exposing step is executed using an etchant comprising sulfuric acid.
- 37. A process as claimed in claim 32 wherein the exposing step is executed using an etchant comprising water, sulfamic acid, and iron (III) chloride.
- 38. A process as claimed in claim 37 wherein the etchant further comprises a weak acid selected from the group consisting of acetic acid, buteric acid, formic acid, and propionic acid.
- 39. A process as claimed in claim 37 wherein the etchant further comprises a surfactant.
- 40. A process as claimed in claim 37 wherein the etchant further comprises diethylene glycol butyl ether.
- 41. In a process for manufacturing a microelectronic interconnect or component formed of copper on a surface of a workpiece, the process comprising the steps of:
depositing a layer of titanium nitride as a copper barrier layer; selectively etching the layer of titanium nitride using an etchant.
- 42. A process as claimed in claim 41 wherein the etchant comprises sulfuric acid and deionized water.
- 43. A process as claimed in claim 41 wherein the etchant comprises hydrofluoric acid and deionized water.
- 44. A process as claimed in claim 42 wherein the etchant further comprises hydrogen peroxide.
- 45. A process as claimed in claim 41 wherein the etchant comprises hydrofluoric acid and deionized water.
- 46. A process as claimed in claim 41 wherein the etchant comprises ammonium hydroxide and deionized water.
- 47. A process as claimed in claim 46 wherein the etchant further comprises hydrogen peroxide.
- 48. A process as claimed in claim 32 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising sulfuric acid, hydrochloric acid, and water.
- 49. A process as claimed in claim 32 wherein the thin-film layer is copper and the etching step is executed using an etchant comprising 1-5% sulfuric acid by volume, 0.1-0.5% hydrochloric acid by volume, and water.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. Ser. No. 09/076,565, filed May 12, 1998, (Attorney Docket No. SEM4492P0051US) and a continuation-in-part of U.S. Ser. No. 09/041,901, filed Mar. 13, 1998 (Attorney Docket No. SEM4492P0040US).
Continuations (1)
|
Number |
Date |
Country |
Parent |
09160522 |
Sep 1998 |
US |
Child |
09999112 |
Nov 2001 |
US |
Continuation in Parts (2)
|
Number |
Date |
Country |
Parent |
09076565 |
May 1998 |
US |
Child |
09160522 |
Sep 1998 |
US |
Parent |
09041901 |
Mar 1998 |
US |
Child |
09160522 |
Sep 1998 |
US |