Patent Application
20080054461
This invention relates to semiconductor fabrication, and more specifically to a method for fabricating solder bumped wafer-level chip-scale packages (WLCSPs).
WLCSPs generally use a metal layer to redistribute very fine-pitch peripheral-arrayed pads on a chip to much larger pitch area-arrayed pads with tall solder joints on the substrate. As a result, solder joint reliability is one of the most critical issues faced during WLCSP fabrication. The present invention is directed toward a new and high-throughput process for assembling WLCSPs on a substrate featuring highly reliable solder joints and protection from moisture penetration.
There exists a number of U.S. patents directed to improving the reliability of WLCSPs, including U.S. Pat. No. 6,287,893 issued to Elenius, et. al. Elenius teaches a chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. Elenius teaches the use of only one, non-conducting layer to cover redistribution lines.
U.S. Pat. No. 6,821,876 issued to Yang, et. al. teaches a fabrication method for strengthening flip-chip solder bumps to form a solder bump on a UBM (under bump metallurgy) structure formed over a semiconductor chip, which can prevent the UBM structure against oxidation and contamination and also enhance bondability between the solder bump and UBM structure. This fabrication method is characterized in that before forming the solder bump, a dielectric layer made of BCB (benzo-cyclo-butene) or polyimide is deposited on the UBM structure, and used to protect the UBM structure against oxidation and contamination. Further, before forming the solder bump, a plasma-etching process is performed to remove the dielectric layer. Yang does not teach a fabrication process that includes non-conductive layers in the final structure.
A process for fabricating reliable solder bumped wafer-level chip-scale packages where the bumps exhibit superior adhesion to the die, minimal resistance, and improved protection from moisture penetration is desired in the art.
The invention comprises, in one form thereof, a packaged semiconductor device including a semiconductor die having at least one conductive bond pad formed upon a surface of the semiconductor die and a patterned first metallization layer disposed above the surface which provides at least one solder bump pad upon the surface, and electrically couples the at least one conductive bond pad to the at least one solder bump pad. The device also includes a patterned first non-conductive layer above first metallization layer, a patterned under bump metallization (UBM) layer above the first metallization layer and the first non-conductive layer, and a patterned second non-conductive layer over the front surface of the semiconductor wafer and above each of the first metallization layer, the first non-conductive layer, and the UBM layer. The device further includes a solder ball connection elements formed on each region of the UBM layer and encapsulation material around the semiconductor die except for at least a portion of each of the solder balls.
The invention further comprises, in one form thereof, a method of fabricating a packaged semiconductor by forming a first metallization layer on a surface of a semiconductor wafer, selectively removing portions of the first metallization layer to provide a plurality of solder bump pads. Then forming a like plurality of first non-conductive regions over each of the plurality of solder bump pads, each of the first non-conductive regions having openings to a portion of a corresponding one of the solder bump pads, forming under bump metallurgical (UBM) regions over each of the openings and over a portion of a corresponding one of the first non-conductive regions, and forming a like plurality of second non-conductive regions over at least a portion of each of the first non-conductive regions, and over an outer portion of each of the UBM regions. Then forming solder balls above each of the solder bump pads, dicing the semiconductor wafer to provide individual integrated circuits and encapsulating at least some of the integrated circuits in an encapsulation material leaving unencapsulated at least a portion of each of the solder balls on the at least some of the individual integrated circuits.
The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:
It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention.
Referring to
The WLCSP solder bump structure 10 may be formed by first depositing the top metallization layer 20, then masking and etching the layer to form the desired metallization pattern. The top metallization layer 20 (which may sometimes be considered a seed layer) may be aluminum or other metals. The top metallization layer 20 is then coated with a first non-conductive layer applied over the front (top) surface of semiconductor wafer 14. The first non-conductive layer (which may sometimes be considered a passivation layer) may be comprised of polyimide, BCB, silicon dioxide, silicon nitride, or other materials known to those skilled in the art. The first non-conductive layer is then patterned to form the first non-conductive layer 22 which allows access to first metal layer 20. Conventional photolithography techniques may be used to form the patterned openings.
The wafer 14 with aluminum layer 20 and first non-conductive layer 22 is then coated with UBM metallization which will form the UBM layer 24. In one embodiment of the present invention, this layer is formed by sputtering onto the wafer 14 between 1000 and 2400 angstroms of Ti followed by between 500 and 3300 angstroms of Ni. This Ti—Ni metallization layer is then masked or etched in one photo process to leave the UBM layer 24 partially covering the first metallization layer 20, and partially overlapping onto the first non-conductive passivation layer 22.
This UBM layer 24 may be a double or triple-metal stack. Other metals which may be used for the UBM layer 24 besides Ti—Ni include, but are not limited to, combinations of Ti, Ni, Au, Cu, or V. For example: Ti—Ni—Au, Ti—Ni—Cu, Ti—Ni—Cu—Au, Al, TiW—Al, Ti—Al, Ti—TiW—Al, Ti—Cu, Ti—Ni—Ag, Ni—V, TiW—Ni—Cu, or Ti—Ni—V. The selected metal(s) should have good adhesion to the first metallization layer 20. The UBM layer 24 serves one or more of the following purposes: (a) it adheres to the underlying surfaces; (b) it acts as a solder diffusion barrier for inhibiting molten solder from passing into the front surface of semiconductor wafer 14; (c) it serves as a “wettable” layer for solderability purposes; and (d) it serves to minimize electrical contact resistance between the solder ball 28 and the conductive bond pad.
The wafer 14 is then coated with a second non-conductive layer. In one embodiment of the invention the second non-conductive layer is of 1 to 6 microns in thickness, and may be polyimide, BCB, silicon dioxide, silicon nitride, or other materials known to those skilled in the art. Contact openings in this second non-conductive layer are made in one photo step by either etching or photo developing to form the second non-conductive layer 26. These openings overlap outer edge of the UBM layer 24, sealing the edge of the metal.
The stack now has metal contacts upon which the solder ball or bump 28 can be formed by several methods. These methods include, but are not limited to, screen printing solder paste/reflow, electro plating solder, or solder ball attach/reflow. After the wafer level chip scale package is formed (as shown in
In the embodiment shown in
In practice, the covering of the second non-conductive layer 44 (which, in one or more embodiments, is polyimide) by the first non-conductive layer 20 followed by electroless nickel plating of the UBM layer 44 results in a thin first non-conductive layer 22 that is protected by the second non-conductive layer 42 from moisture penetration, and promotes adhesion of the UBM layer 44 to the wafer 14.
In the embodiment shown in
In alternative embodiments of the present invention an electroless gold layer may be used instead of the electroless nickel layers.
While the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof to adapt to particular situations without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/841,100, filed Aug. 30, 2006, which is hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60841100 | Aug 2006 | US |
