Claims
- 1. A semiconductor device, comprising:
a mounting substrate; a first semiconductor device including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.
- 2. A semiconductor device according to claim 1, wherein the first semiconductor chip is a semiconductor chip including a memory, and the second semiconductor chip is a semiconductor chip including a controller.
- 3. A semiconductor device according to claim 2, wherein the memory in the first semiconductor chip is a dynamic random access memory.
- 4. A semiconductor device according to claim 1, further comprising an elastic layer positioned between the main surface of the first semiconductor chip and the plurality of bump electrodes.
- 5. A semiconductor device according to claim 1,
wherein the first semiconductor chip has a plurality of external terminals electrically connected to corresponding ones of the plurality of bump electrodes, respectively, and wherein the minimum interval of the plurality of bump electrodes is wider than the minimum interval of the plurality of external terminals of the first semiconductor chip.
- 6. A semiconductor device according to claim 1,
wherein the first semiconductor chip has a row of external terminals electrically connected to the plurality of bump electrodes, and wherein the plurality of bump electrodes includes an array of bump electrodes at each of two opposing sides of the row of external terminals.
- 7. A semiconductor device according to claim 1, wherein the mounting substrate, and the first and second devices comprise a memory card.
- 8. A semiconductor device according to claim 1, further comprising a third semiconductor device, the third semiconductor device including a third semiconductor chip and a plurality of bump electrodes, the third semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the third semiconductor chip, and the third semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes.
- 9. A semiconductor device according to claim 8, wherein the first semiconductor chip and the third semiconductor chip are semiconductor chips including a memory, respectively.
- 10. A semiconductor device according to claim 9, wherein the second semiconductor chip is a semiconductor chip including a controller.
- 11. A semiconductor device according to claim 10, wherein the memory in the first and in the third semiconductor chip is a dynamic random access memory, respectively.
- 12. A semiconductor device according to claim 9, wherein the memory in the first and in the third semiconductor chip is a dynamic random access memory, respectively.
- 13. A semiconductor device according to claim 8,
wherein each of the first and third semiconductor chips has a plurality of external terminals electrically connected to corresponding ones of the plurality of bump electrodes, respectively, and wherein the minimum interval of the plurality of bump electrodes is wider than the minimum interval of the plurality of external terminals corresponding to each of the first and third semiconductor chips.
- 14. A semiconductor device according to claim 8,
wherein each of the first and third semiconductor chips has a row of external terminals electrically connected to the plurality of bump electrodes corresponding thereto, and wherein the plurality of bump electrodes in each of the first and third semiconductor chips includes an array of bump electrodes at each of two opposing sides of the row of external terminals thereof.
- 15. A semiconductor device according to claim 8, wherein the mounting substrate, and the first, second and third semiconductor devices comprise a memory card.
- 16. A composite device, comprising:
a mounting substrate having a quadrilateral shaped main surface, and external connection terminals, located at one of the four end sides thereof, to retractably mount the device to an electrical equipment; at least one first semiconductor device each including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.
- 17. A composite device according to claim 16,
wherein each first semiconductor chip is a memory chip and the second semiconductor chip includes a controller, and wherein the first and second semiconductor devices and mounting substrate comprise a memory card.
- 18. A composite device, comprising:
a mounting substrate; a plurality of first semiconductor devices arrayed on a main surface of the mounting substrate, each first semiconductor device including a first semiconductor chip and a plurality of bump electrodes, the first semiconductor chip having a plurality of semiconductor elements on a main surface thereof, the plurality of bump electrodes being disposed on the main surface of the first semiconductor chip, and the first semiconductor device being mounted on the mounting substrate through the plurality of bump electrodes; and a second semiconductor device including a second semiconductor chip, a sealing member and a plurality of leads, the sealing member having an upper surface, a rear surface opposite to the upper surface and a side surface between the upper and rear surfaces, the plurality of leads protruding outwardly from a side surface of the sealing member, and the second semiconductor device being mounted on the mounting substrate through the plurality of leads.
- 19. A composite device according to claim 18,
wherein each first semiconductor chip is a random access memory chip and the second semiconductor chip includes a controller, and wherein the first and second semiconductor devices and mounting substrate comprise a memory card.
- 20. A composite device according to claim 18, further comprising an elastic layer positioned between the main surface of each of the first semiconductor chips and the plurality of bump electrodes corresponding thereto.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-66637 |
Mar 1996 |
JP |
|
Parent Case Info
[0001] This is a division of U.S. Ser. No. 09/449,834, filed Nov. 26, 1999, which, in turn, is a continuation of U.S. Ser. No. 08/822,833, filed Mar. 21, 1997, and the disclosures of which are incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09449834 |
Nov 1999 |
US |
Child |
09771985 |
Jan 2001 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
08822833 |
Mar 1997 |
US |
Child |
09449834 |
Nov 1999 |
US |