Patent Application
20090108447
This application claims the benefit of Korean Patent Application No. 10-2007-0107816, filed on Oct. 25, 2007, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference.
The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device, such as a semiconductor chip, a semiconductor package, or a semiconductor module, having fine pitch bond pads and also having a sufficient adhesive strength between bond pads and ball bonds.
In the past, semiconductor packaging technology was developed by focusing on how to route signal lines in a semiconductor chip to the outside how to effectively transfer heat generated in the semiconductor chip to the outside, and how to effectively protect the semiconductor chip from external impact.
Early semiconductor packages were developed as insertion semiconductor packages, such as dual in-line packages (DIPs), and surface mounting semiconductor packages, such as thin quad flat packages (TQFPs) and thin small out-line packages (TSOPs), these packages including pin grid arrays (PGAs) with fine pitches.
Currently, semiconductor packages are developed with a focus on high integration in light, thin, and small semiconductor packages to cope with the miniaturization of electronic products. Accordingly, semiconductor packages are being developed into ball grid arrays (BGAs) using solder balls or bumps as external connection terminals, chip scale packages (CSPs), and wafer level packages (WLPs). However, continued development of semiconductor packages is advancing to develop packages with complicated structures, such as, multi-chip packages (MCPs), multi-chip modules (MCMs), and system in packages (SIPs).
There are two classifications of interconnection techniques used in MCPs, MCMs, and SIPs: flip-chip, and non-flip-chip packaging techniques. The flip-chip packaging technique achieves interconnection by using bumps, but the non-flip chip packaging technique does not. Most non-flip chip packaging techniques us wire bonding as the interconnection technique within a semiconductor package.
In semiconductor packages such as BGAs, MCPs, and SIPs, the number of input/output (I/O) terminals in a semiconductor chip increases in accordance with the trend toward miniaturization and high integration. As such, the realization of a fine pitch for bond pads in semiconductor chips used in non-flip chip packages becomes an essential technique for the development of these advanced semiconductor packages.
Embodiments of the present inventive concept provide a semiconductor device having fine pitch bond pads in which an interval between bond pads may be reduced while preventing a reduction of the area where wire bonding is performed. These embodiments help reduce adhesion between ball bonds.
An embodiment of the present inventive concept includes a semiconductor device comprising bond pads, a semiconductor chip, fine pitch bond pads, and dummy pads. The fine pitch bond pads are formed on the semiconductor chip and are electrically connected to circuits in the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each ball bond. The dummy bond pads are formed between adjacent bond pads on the semiconductor chip, and are not electrically connected to the semiconductor chip circuits.
The above and other features and advantages of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
The present embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown.
The semiconductor device 200 according to the current embodiment also includes dummy bond pads 104 which are each formed between adjacent bond pads 102 and are not connected to the circuit lines 106. Similar to bond pads 102, each of the dummy bond pads 104 includes a plurality of small lands 112 that are separated from each other.
The semiconductor device 200 according to the current embodiment may include a passivation layer 114, which is used as a final film for protecting a semiconductor chip, and is formed in a circuit region instead of the region 110 that includes the bond pads 102 and the dummy bond pads 104.
Alternatively, the semiconductor device 200 may have passivation layer 114 formed between the bond pads 102 as in a conventional bond pad configuration. The small lands 112 of each of the dummy bond pads 104 may be formed at regular intervals between the bond pads 102. The lands 108 of the bond pads 102 and the lands 112 of the dummy bond pads 104 may be designed to have different shapes or colors so that the bond pads 102 and the dummy bond pads 104 can be easily distinguished from each other. The functions of the dummy bond pads 104 will be described later with reference to
As in the embodiment of
Referring to
The semiconductor device 202 according to the current embodiment may be an advanced semiconductor package, such as a ball grid array (BGA), a multi-chip package (MCP), a system in package (SIP), or a memory module such as a multi-chip module (MCM). In
The semiconductor device 202 according to the current embodiment includes spaces between the bond pads 102 where the dummy bond pads 104 may be arranged. Accordingly, the fine pitch bond pads 102 may be formed by setting the width W of each bond pad 102 to be less than the caliber of each ball bond 118. Therefore, two adjacent ball bonds 118 share a space between bond pads 102 at a predetermined ratio and accordingly use the space as a wire bonding space. However, since the dummy bond pads 104 are connected to the adjacent ball bonds 118 and are each comprised of a plurality of small lands 112 that are separated from each other, the dummy bond pads 104 do not cause an electrical short circuit therebetween.
In general, when the width W of each bond pad 102 is less than the width of each ball bond 118, defective semiconductor devices are detected in, for example, a bond pull test (BPT) or a bond shear test (BST). The BPT is a reliability test where the adhesive strength between the bond pads 102 and the ball bonds 118 is checked by pulling the wires 116 up with a predetermined force. The BST is a reliability test where the adhesive strength between the bond pads 102 and the ball bonds 118 is checked by pulling the ball bonds 118 sideways. It is therefore more difficult to design the bond pads 102 than the ball bonds 118 because when the bond pads 102 do not sufficiently adhere to the ball bonds 118, a large number of defective semiconductor devices may be detected in a reliability test.
However, the current embodiment of
When the dummy bond pads 104 are arranged between adjacent bond pads 102, it is therefore expected that a pitch B between bond pads 102 can be designed about 23% smaller than the pitch A between conventional bond pads 10 of
The lands 108 of the bond pads 102 and the lands 112 of the dummy bond pads 104 may be designed to have different shapes and colors so that occurrence or non-occurrence of electrical short-circuits can be easily and visually determined. Although the rectangular lands 108 and 112 are illustrated in
Referring to
As in
According to an embodiment of the inventive concept, a plurality of small dummy bond pads are formed between bond pads, and portions of ball bonds are located over the small dummy bond pads during wire bonding. The fine pitch bond pads are capable of preventing electrical short-circuits between adjacent ball bonds. Consequently, although the number of I/O terminals in advanced semiconductor packages may increase, bond pads having fine pitches can be efficiently formed.
In addition, the small dummy bond pads arranged between bond pads increase adhesive strength of bond pads that have widths less than the diameters of the ball bonds. Thus, although the pitch between bond pads decreases, reliable bondability is maintained.
Moreover, the dummy bond pads and the bond pads are designed to have different shapes and colors. Thus, electrical short-circuits between adjacent ball bonds can be easily monitored.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-0107816 | Oct 2007 | KR | national |
