Patent Application
20250015063
This application is based on and claims priority to Korean Patent Application No. 10-2023-0087270, filed on Jul. 5, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
Embodiments of the present application relate to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including a redistribution substrate and a method of manufacturing the semiconductor package.
As the electronics industry advances rapidly and the demands of users increase, electronic devices are being more and more miniaturized and light. As electronic devices are miniaturized and light, semiconductor packages are being miniaturized and made light and moreover need high performance, large capacity, and high reliability. As the high performance and large capacity of semiconductor packages are implemented, the power consumption of semiconductor packages is increasing. Therefore, the size/performance and heat dissipation characteristics of semiconductor packages are increasing in significance.
One or more embodiments provide a semiconductor package and a method of manufacturing the same, in which structural reliability is enhanced.
According to an aspect of an embodiment, there is provided a semiconductor package including a redistribution substrate, a first semiconductor chip on the redistribution substrate, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in a horizontal direction, a third semiconductor chip on the second semiconductor chip, and a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, wherein the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction, and wherein a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip.
According to another aspect of an embodiment, there is provided a semiconductor package including a redistribution substrate, a first semiconductor chip on the redistribution substrate, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in a horizontal direction, a third semiconductor chip on the second semiconductor chip, a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, a fourth semiconductor chip between the first semiconductor chip and the heat dissipation chip, and a sealant on the redistribution substrate and on a side surface of the first semiconductor chip, a side surface of the second semiconductor chip, and a side surface the fourth semiconductor chip, wherein the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction, and wherein a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip.
According to another aspect of an embodiment, there is provided a semiconductor package including a redistribution substrate including one or more redistribution insulation layers stacked in a vertical direction, a redistribution line extending in a horizontal direction in the one or more redistribution insulation layers, and a redistribution via extending in the vertical direction in each of the one or more redistribution insulation layers, a first semiconductor chip on the redistribution substrate, the first semiconductor chip including a first substrate and a first chip pad, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in the horizontal direction, the second semiconductor chip including a second substrate, a second chip pad, and a plurality of through vias passing through at least a portion of the second substrate in the vertical direction, a third semiconductor chip on the second semiconductor chip, a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, a first connector between the first semiconductor chip and the redistribution substrate, a second connector between the second semiconductor chip and the redistribution substrate, a third connector between the third semiconductor chip and the second semiconductor chip, and a heat dissipation connector between the heat dissipation chip and the first semiconductor chip, the heat dissipation connector including a metal pad and an adhesive layer.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements in the drawings, and their repeated descriptions are omitted. Embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto.
It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and/or sections (collectively “elements”), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element described in this description section may be termed a second element or vice versa in the claim section without departing from the teachings of the disclosure.
It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
Herein, a direction parallel to a main surface of the redistribution substrate 110 may be defined as the horizontal direction (the X direction and/or the Y direction), and a direction perpendicular to the horizontal direction (the X direction and/or the Y direction) may be defined as a vertical direction (a Z direction).
Referring to
The redistribution substrate 110 may be disposed under the semiconductor package 100. The redistribution substrate 110 may be disposed under the first semiconductor chip 120, the second semiconductor chip 130, and the sealant 170. The redistribution substrate 110 may redistribute a first chip pad 124 of the first semiconductor chip 120 to an external region of the first semiconductor chip 120. Also, the redistribution substrate 110 may redistribute a second chip pad 136 of the second semiconductor chip 130 to an external region of the second semiconductor chip 130.
The redistribution substrate 110 may include a redistribution insulation layer 112, a redistribution line 114, and a redistribution via 116. The redistribution insulation layer 112 may include an insulating material (for example, a photo imageable dielectric (PID) or a photo imageable polyimide (PIP), and may further include an inorganic filler. However, a material of the redistribution insulation layer 112 is not limited to materials described above. For example, the redistribution insulation layer 112 may include polyimide isoindro quirazorindione (PIQ), polyimide (PI), or polybenzoxazole (PBO).
The redistribution insulation layer 112 may have a multilayer structure, based on a multilayer structure of the redistribution line 114. All layers of the redistribution insulation layer 112 may include the same material, or at least one layer may include a different material.
The redistribution line 114 may be disposed as a multilayer in the redistribution insulation layer 112. Redistribution lines 114 disposed in different layers may be connected with each other by the redistribution via 116. The redistribution line 114 and the redistribution via 116 may include, for example, copper (Cu). However, a material of each of the redistribution line 114 and the redistribution via 116 is not limited to Cu.
An upper pad 118 may be disposed on an upper surface of an uppermost redistribution insulation layer 112. The upper pad 118 may be a separate element independent of the redistribution line 114. In other embodiments, the upper pad 118 may be provided as a portion of the redistribution line 114.
The upper pad 118 may be electrically connected with the redistribution line 114 and the redistribution via 116. Therefore, the upper pad 118 may electrically connect each of the first semiconductor chip 120 and the second semiconductor chip 130 with the redistribution substrate 110. The upper pad 118 may contact a first connector 125 and/or a second connector 137.
An external connection terminal 119 may be disposed on a lower surface of a lowermost redistribution insulation layer 112. The external connection terminal 119 may be disposed on a lower pad formed on the lower surface of the lowermost redistribution insulation layer 112. The lower pad may be referred to as an external connection pad. The external connection pad may be provided as a portion of the redistribution line 114. However, in an embodiment, the external connection pad may be provided as a separate element independent of the redistribution line 114.
The external connection terminal 119 may be electrically connected with the redistribution line 114 through the external connection pad. Therefore, the external connection terminal 119 may be electrically connected with the first semiconductor chip 120 through the redistribution line 114, the redistribution via 116, the upper pad 118, and the first connector 125 of the redistribution substrate 110. Also, the external connection terminal 119 may be electrically connected with the second semiconductor chip 130 through the redistribution line 114, the redistribution via 116, the upper pad 118, and the second connector 137 of the redistribution substrate 110. Also, the external connection terminal 119 may connect the semiconductor package 100 with a package substrate of an external system or a main board of an electronic device such as a mobile device. The external connection terminal 119 may include a conductive material, and for example, may include at least one of a solder, tin (Sn), silver (Ag), Cu, and aluminum (Ag). However, a material of the external connection terminal 119 is not limited to materials described above.
The external connection terminal 119 may be disposed in a region which is greater than the size of each of the first semiconductor chip 120 and the second semiconductor chip 130 in a horizontal direction (an X direction and/or a Y direction). As described above, a package structure where the external connection terminal 119 is disposed in a region which is greater than the size of each of the first semiconductor chip 120 and the second semiconductor chip 130 may be referred to as a fan-out (FO) package. A package structure where the external connection terminal 119 is disposed at only a portion corresponding to a lower surface of each of the first semiconductor chip 120 and the second semiconductor chip 130 may be referred to as a fan-in (FI) package structure.
Each of the first semiconductor chip 120 and the second semiconductor chip 130 may be disposed on the redistribution substrate 110. The first semiconductor chip 120 and the second semiconductor chip 130 may be spaced apart from each other in the horizontal direction (an X direction and/or a Y direction). The first semiconductor chip 120 may be mounted on the redistribution substrate 110 through the first connector 125, and the second semiconductor chip 130 may be mounted on the redistribution substrate 110 through the second connector 137. The first and second connectors 125 and 137 may each include a solder ball and/or a pillar. A pillar may include, for example, Cu. However, a material of the pillar is not limited to Cu.
The first semiconductor chip 120 may be an analog chip. The first semiconductor chip 120 may include a plurality of logic devices. Here, the logic devices may be devices for performing various signal processing, and for example, may include an AND gate, an OR gate, a NOT gate, and a flip-flop. The logic devices may include devices for supporting communication. In the semiconductor package 100 according to an embodiment, the first semiconductor chip 120 may be, for example, an application processor (AP) chip. The first semiconductor chip 120 may be referred to as a control chip, a process chip, or a central processing unit (CPU) chip based on a function thereof. Also, in terms of an integrated function, the first semiconductor chip 120 may be referred to as a system on chip (SoC). Furthermore, according to an embodiment, devices for supporting communication may be separately provided as another chip (for example, a modem chip) and may be disposed on the redistribution substrate 110 in a structure coupled to the first semiconductor chip 120.
The second semiconductor chip 130 may be, for example, a silicon (Si) chip. Devices or wirings may not be formed in the second semiconductor chip 130. Generally, the stiffness of Si may be higher than that of resin (for example, an epoxy mold compound (EMC)) included in the sealant 170. Therefore, the second semiconductor chip 130 may increase a resistance to warpage of the semiconductor package 100.
Although in
The first semiconductor chip 120 may include a first substrate 122 and a first chip pad 124. The second semiconductor chip 130 may include a second substrate 132, a through electrode 134, and a second chip pad 136. The first substrate 122 may include an active surface and an inactive surface, which are opposite to each other. In the first substrate 122, the active surface may be disposed adjacent to a lower surface of the first substrate 122, and the inactive surface may be disposed adjacent to an upper surface of the first substrate 122.
Each of the first substrate 122 and the second substrate 132 may include a semiconductor material, and for example, may include Group IV semiconductor material, Group III-V semiconductor material, Group II-VI semiconductor material, or a combination thereof. The Group IV semiconductor material may include, for example, Si, germanium (Ge), or a combination thereof. The Group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), indium gallium arsenide (InGaAs), or a combination thereof. The Group II-VI semiconductor material may include, for example, zinc tellurium (ZnTe), cadmium sulfur (CdS), or a combination thereof.
The first and second chip pads 124 and 136 may be respectively disposed on lower surfaces of the first substrate 122 and the second substrate 132 and may respectively extend along the lower surfaces of the first substrate 122 and the second substrate 132. Also, the first connector 125 may be disposed between the first semiconductor chip 120 and the redistribution substrate 110, and the second connector 127 may be disposed between the second semiconductor chip 130 and the redistribution substrate 110.
The through electrode 134 may be a through silicon via (TSV) passing through Si of the second semiconductor chip 130. The through electrode 134 may pass through at least a portion of the second substrate 132 of the second semiconductor chip 130 in the vertical direction (the Z direction). The through electrode 134 may electrically connect the redistribution substrate 110 with the third semiconductor chip 140. The through electrode 134 may electrically connect the second chip pad 136 of the second semiconductor chip 130 with the third connector 145. For example, a lower surface of the through electrode 134 may contact the second chip pad 136, and an upper surface of the through electrode 134 may contact the third connector 145.
The third semiconductor chip 140 may be disposed on the second semiconductor chip 130. The third semiconductor chip 140 may be disposed on the second semiconductor chip 130 through the third connector 145. The third semiconductor chip 140 may be a memory chip. Therefore, the third semiconductor chip 140 may include a plurality of memory devices. The third semiconductor chip 140 may include, for example, a volatile memory device such as dynamic random access memory (DRAM) or static random access memory (SRAM) or a non-volatile memory device such as flash memory. In the semiconductor package 100 according to an embodiment, the third semiconductor chip 140 may include, for example, a DRAM device.
In some embodiments, the third semiconductor chip 140 may be stacked on the second semiconductor chip 130 on which a memory device, having a package structure where a plurality of memory chips are stacked, is stacked. As described above, in a case where a memory device having a package structure is stacked on the second semiconductor chip 130, all semiconductor packages may correspond to a package on package (POP) structure. A semiconductor package having the POP structure will be described below in more detail in describing
The third connector 145 may be disposed between the second semiconductor chip 130 and the third semiconductor chip 140. The third connector 145 may be disposed between a third chip pad of the third semiconductor chip 140 and an upper surface of the through electrode 134 corresponding thereto. According to an embodiment, a pad may be formed on the through electrode 134, and the third connector 145 may be disposed between the third chip pad and the pad corresponding thereto. The third connector 145 may include a solder ball and/or a pillar. Furthermore, an underfill UF may be filled between the third semiconductor chip 140 and the sealant 170. According to an embodiment, the underfill UF may be omitted.
The heat dissipation chip 150 may be disposed on the first semiconductor chip 120. The heat dissipation chip 150 may be stacked on the first semiconductor chip 120 through the heat dissipation connection unit 160. The heat dissipation chip 150 may be, for example, Si. Devices or wirings may not be formed in the heat dissipation chip 150. Generally, a thermal conductance of Si may be higher than that of resin (for example, an EMC) included in the sealant 170. Accordingly, the heat dissipation chip 150 may more efficiently dissipate heat occurring in the first semiconductor chip 120.
The heat dissipation connector 160 may be disposed between the first semiconductor chip 120 and the heat dissipation chip 150. The heat dissipation connector 160 may include a metal pad 162 and an adhesive layer 164. The metal pad 162 may be disposed on a lower surface of the heat dissipation chip 150 and may include metal having a high thermal conductance. For example, the metal pad 162 may include Cu, nickel (Ni), aluminum (Al), Sn, gold (Au), or Ag. However, a material of the metal pad 162 is not limited to describe above. Furthermore, according to an embodiment, the heat dissipation chip 150 may include a passivation layer on a lower surface thereof, and the metal pad 162 may be disposed on a lower surface of the heat dissipation chip 150 in a type passing through the passivation layer. The passivation layer may include, for example, silicon oxide or silicon nitride.
The adhesive layer 164 may attach and fix the heat dissipation chip 150 on and to the first semiconductor chip 120. As illustrated in
As illustrated in
The sealant 170 may be disposed between the redistribution substrate 110 and the third semiconductor chip 140 and may be disposed between the redistribution substrate 110 and the heat dissipation chip 150. The sealant 170 may expose the upper surface of the first semiconductor chip 120 and/or the second semiconductor chip 130. The sealant 170 may cover and seal side surfaces of the first semiconductor chip 120 and the second semiconductor chip 130. As illustrated in
Also, an upper surface of the sealant 170 may be at the same vertical level as each of the upper surface of the first semiconductor chip 120 and the upper surface of the second semiconductor chip 130 or horizontally aligned with the upper surface of the first semiconductor chip 120 and the upper surface of the second semiconductor chip 130. For example, the upper surface of the first semiconductor chip 120 and the upper surface of the second semiconductor chip 130 may not be sealed by the sealant 170.
The sealant 170 may include an insulating material, and for example, may include thermo-curable resin such as epoxy resin, thermo-plastic resin such as polyimide, or resin where a stiffener such as an inorganic filler is included therein. For example, the sealant 170 may include Ajinomoto build-up film (ABF), frame retardant 4 (FR-4), or bismaleimide triazine (BT) resin. Also, the sealant 170 may include a molding material such as EMC or a photosensitive material such as photo imageable encapsulant (PIE). However, a material of the sealant 170 is not limited to materials described above.
A position relationship and one-dimensional sizes of the redistribution substrate 110, the first to third semiconductor chips 120 to 140, and the heat dissipation chip 150, the redistribution substrate 110 may one-dimensionally have substantially the same size as that of the sealant 170. Therefore, in a plan view, the first semiconductor chip 120 and the second semiconductor chip 130 may be disposed in the redistribution substrate 110. Also, in a plan view, the third semiconductor chip 140 and the heat dissipation chip 150 each disposed on the first semiconductor chip 120 and the second semiconductor chip 130 may be disposed in the redistribution substrate 110. The third semiconductor chip 140 and the heat dissipation chip 150 may be spaced apart from each other in the horizontal direction (the X direction and/or the Y direction), on the sealant 170.
The first semiconductor chip 120 may overlap the heat dissipation chip 150 in the vertical direction (the Z direction), and the second semiconductor chip 130 may overlap the third semiconductor chip 140 in the vertical direction (the Z direction). In a plan view, the first semiconductor chip 120 and the third semiconductor chip 140 may be disposed apart from each other in the horizontal direction (the X direction and/or the Y direction), and the second semiconductor chip 130 and the heat dissipation chip 150 may be disposed apart from each other in the horizontal direction (the X direction and/or the Y direction).
In the semiconductor package 100 according to an embodiment, the first semiconductor chip 120 and the second semiconductor chip 130 may be self-aligned and disposed on the redistribution substrate 110. Therefore, the redistribution line 114 of the redistribution substrate 110 may include a fine line and space L/S. For example, the uppermost redistribution line 114 connected with the first connector 125 of the first semiconductor chip 120 may have a line width and interval of 2/2 μm. Also, redistribution lines 114 under the uppermost redistribution line 114 may have, for example, a line width and interval of 7/8 μm. A method of self-aligning the first semiconductor chip 120 and the second semiconductor chip 130 will be described in more detail in describing a method of manufacturing a semiconductor package illustrated in
Referring to
The heat dissipation chip 150a may include a plurality of metal lines 155 which pass through at least a portion of the heat dissipation chip 150a in a vertical direction (a Z direction). The metal line 155 may include metal having a high thermal conductance. For example, the metal line 155 may include Cu, Ni, Al, Sn, Au, or Ag. However, a material of the metal line 155 is not limited to describe above.
The metal line 155 may be higher in thermal conductance than Si of the heat dissipation chip 150a and may thus more efficiently dissipate heat from the first semiconductor chip 120 to the outside of the semiconductor package 100a. The metal line 155 may be connected with a metal pad 162 disposed under the heat dissipation chip 150a. However, at least a portion of the metal line 155 may not be connected with the metal pad 162.
Referring to
The memory device 140a may be disposed on the second semiconductor chip 130. The memory device 140a may be electrically connected with the redistribution substrate 110 through a through electrode 134 of the second semiconductor chip 130. For example, the memory device 140a may be a high bandwidth memory (HBM) package. To provide a more detailed description, the memory device 140a, which is an HBM package, may include a base chip 142, a plurality of core chips 144, an internal sealant 146, and a memory device through electrode 148.
The base chip 142 may include logic devices. Therefore, the base chip 142 may be a logic chip. The base chip 142 may be disposed under the core chips 144 and may integrated and transfer signals of the core chips 144 to the outside, and moreover, may transfer a signal and power from the outside to the core chips 144. Therefore, the base chip 142 may be referred to as a buffer chip or a control chip. Furthermore, each of the core chips 144 may be a memory chip. For example, each of the core chips 144 may be a DRAM chip. Also, the core chip 144 may be stacked on the base chip 142 or a lower core chip 144 through pad-to-pad bonding, hybrid bonding (HB), bonding using a bonding member, or bonding using an anisotropic conductive film (ACF). In
The core chips 144 on the base chip 142 may be sealed by the internal sealant 146. However, an uppermost core chip 144 of the core chips 144 may not be covered by the internal sealant 146. In other embodiments, an upper surface of the uppermost core chip 144 may be covered by the internal sealant 146.
The base chip 142 and the core chips 144 may include a memory device through electrode 148. Here, the memory device through electrode 148 may be a TSV. As illustrated in
In the semiconductor package 100b according to an embodiment, the memory device 140a is not limited to the HBM package. For example, the memory device 140a may have a general package structure. For example, the memory device 140a may include an upper package substrate and a plurality of memory chips stacked on the upper package substrate. The upper package substrate may be disposed on the second semiconductor chip 130 through the third connector 145. Also, the memory chips may be stacked on the upper package substrate through a bonding wire or may be stacked on the upper package substrate through a bump and a TSV.
The semiconductor package 100b according to an embodiment may have a POP structure. In detail, the redistribution substrate 110, the first semiconductor chip 120, the second semiconductor chip 130, and the sealant 170 may configure a first package PKG1, and the memory device 140a may configure a second package PKG2. Accordingly, the semiconductor package 100b according to an embodiment may have a POP structure where the second package PKG2 is stacked on the first package PKG1 through the third connector 145.
Referring to
The fourth semiconductor chip 180 may be stacked on the first semiconductor chip 120 through bonding using a bump, bonding using ACF, or HB. For reference, the HB may denote bonding where pad-to-pad bonding and insulator-to-insulator bonding are combined. The ACF may be an anisotropic conductive layer which allows electricity to flow in only one direction and may denote a conductive layer which is formed in a film state by combining a micro conductive particle with adhesive resin.
In
Also, an upper surface of the sealant 170 may be at the same vertical level as each of an upper surface of the second semiconductor chip 130 and an upper surface of the fourth semiconductor chip 180 or horizontally aligned with an upper surface of the second semiconductor chip 130 and an upper surface of the fourth semiconductor chip 180. For example, the upper surface of the second semiconductor chip 130 and the upper surface of the fourth semiconductor chip 180 may not be sealed by the sealant 170.
Referring to
Referring to
The upper sealant 175 may not cover an upper surface of the third semiconductor chip 130 and an upper surface of the heat dissipation chip 150. In other embodiments, the upper sealant 175 may cover the upper surface of the third semiconductor chip 130 and/or the upper surface of the heat dissipation chip 150. In this case, the upper surface of the third semiconductor chip 140 may be at a vertical level which is lower than the upper surface of the heat dissipation chip 150.
Referring to
Referring to
Referring to
One or more redistribution insulation layers 112 may be stacked in a vertical direction (a Z direction). The redistribution line 114 may extend in a horizontal direction (an X direction and/or a Y direction) in the redistribution insulation layer 112. The redistribution via 116 may extend in the vertical direction (the Z direction) in the redistribution insulation layer 112 and may be electrically connected with at least one redistribution line 114.
First, a lowermost conductive line pattern may be formed, and then, a preliminary lowermost redistribution insulation layer covering the lowermost conductive line pattern may be formed. Subsequently, at least a portion of the preliminary lowermost redistribution insulation layer may be removed by performing an exposure process, and thus, a lowermost redistribution insulation layer 112 including a via hole may be formed. A base redistribution conductive layer may be formed on the lowermost redistribution insulation layer 112, and then, by patterning the base redistribution conductive layer, a base conductive pattern including redistribution vias 116 and the redistribution line 114 may be formed. Subsequently, by repeatedly forming the redistribution insulation layer 112 and the conductive patterns, the redistribution substrate 110 may be formed.
Referring to
The first connector 125 and/or the second connector 137 may be self-aligned and connected with the upper pad 118. Therefore, the first connector 125 and/or the second connector 137 may be relatively very small. Based thereon, redistribution lines 114 of the redistribution substrate 110 may be formed to have a relatively fine width and interval. For example, redistribution lines 114 coupled to the first connector 125 of the first semiconductor chip 120 among the redistribution lines 114 of the redistribution substrate 110 may have a line width and interval of 2/2 μm.
Referring to
Referring to
Subsequently, an external connection terminal 119 may be formed on the redistribution substrate 110. The external connection terminal 119 may be substantially the same as the description of the external connection terminal 119 of the semiconductor package 100 of
Referring to
After the external connection terminal 119 is attached on the film frame mount 200, a whole resultant material may be reversed so that the film frame mount 200 is disposed downward, and the second carrier substrate (CA2 of
Referring to
Subsequently, the semiconductor package 100 of
Referring to
After the metal seed layer SL is formed, an upper pad 118 may be formed. A photoresist pattern may be formed on the metal seed layer SL, and then, at least a portion of the metal seed layer SL may be exposed by using the photoresist pattern and the upper pad 118 may be formed by performing a plating process on the exposed metal seed layer SL. The plating process may be, for example, a Cu plating process. However, the plating process is not limited to the Cu plating process.
Therefore, a portion, where the first semiconductor chip 120 is to be disposed, of the upper pad 118 and a portion, where the second semiconductor chip 130 is to be disposed, of the upper pad 118 may differ in dimension.
Referring to
The first connector 125 and/or the second connector 137 may be self-aligned and connected with the upper pad 118. Therefore, the first connector 125 and/or the second connector 137 may be relatively small.
Referring to
Referring to
A method of manufacturing the redistribution substrate 110 may be substantially the same as the method of manufacturing the redistribution substrate 110 of
Subsequently, by performing the same process as the method described above with reference to
Hereinabove, embodiments have been described in the drawings and the specification. Embodiments have been described by using the terms described herein, but this has been merely used for describing the embodiments and has not been used for limiting a meaning or limiting the scope defined in the following claims. Therefore, it may be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments may be implemented from the embodiments. Accordingly, the spirit and scope may be defined based on the spirit and scope of the following claims and their equivalents.
While embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0087270 | Jul 2023 | KR | national |
