Patent Application
20250125280
This application claims the priority and benefit of Korean Patent Application Nos. 10-2023-0137405, filed on Oct. 16, 2023, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present inventive concepts relates to a semiconductor chip, a semiconductor package, and a method of manufacturing a semiconductor chip.
As electronic devices become lighter and are implemented with high performance, miniaturization and high performance are also required in a field of semiconductor packages (e.g., High-Bandwidth Memory, non-memory semiconductor package). An operation of a semiconductor chip that may be included in a semiconductor package (e.g., signal transmission/reception processing, information storage processing, logic operation processing, circuit operation, and the like) may be affected by electromagnetic noise externally of the semiconductor package. Accordingly, the semiconductor package may be more advantageous for miniaturization and high performance by improving electromagnetic shielding reliability.
Some example embodiments of inventive concepts provide a semiconductor package and a method of manufacturing a semiconductor package that can improve electromagnetic shielding reliability.
Some example embodiments of inventive concepts relate to a wiring structure having a structure in which at least one insulating layer and at least one wiring layer are alternately stacked; a semiconductor chip to vertically overlap the wiring structure; and a conductive shielding layer accommodating the semiconductor chip, and covering a portion of a side surface of the wiring structure to be connected to a ground of the at least one wiring layer, wherein another portion of the side surface of the wiring structure may not be covered by the conductive shielding layer.
Some example embodiments of inventive concepts relate to a method of manufacturing a semiconductor package, including disposing a semiconductor package so that the portion of a semiconductor package on which a conductive shielding layer is not formed is immersed in liquid; and forming the conductive shielding layer on another portion of the semiconductor package, such that a portion of the conductive shielding layer covers the another portion of the semiconductor package immersed in liquid.
Some example embodiments of inventive concepts relate to a method of manufacturing a semiconductor package, including disposing a semiconductor package on an upper surface of a film on which a coating layer is formed on a portion of the upper surface, so that a portion of the semiconductor package is in contact with a side surface of the coating layer; and forming a conductive shielding layer to cover another portion of the semiconductor package that is not in contact with the side surface of the coating layer.
The above and other aspects, features, and advantages of the present inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
The detailed description of the present inventive concepts refers to the accompanying drawings which, by way of example, illustrate some example embodiments in which the present inventive concepts may be practiced. These example embodiments are described in sufficient detail to enable one skilled in the art to practice the present inventive concepts. It should be understood that the various example embodiments of the present inventive concepts are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one example embodiment and/or in another example embodiment without departing from the spirit and scope of the inventive concepts. Additionally, it should be understood that the location or arrangement of individual components within each disclosed example embodiment may be changed without departing from the spirit and scope of the inventive concepts. Accordingly, the detailed description set forth below is not to be taken in a limiting sense, and the scope of the present inventive concepts is limited only by the appended claims, along with all equivalents as claimed by those claims. Like reference numbers in the drawings indicate the same or similar function throughout the various aspects.
As described herein, an element that is “on” another element may be above or beneath or adjacent (e.g., horizontally adjacent) to the other element. An element that is on another element may be directly on the other element, such that the element is in direct contact with the other element. An element that is on another element may be indirectly on the other element, such that the element is isolated from direct contact with the other element by one or more interposing spaces and/or structures.
It will be understood that elements and/or properties thereof may be recited herein as being “the same” or “equal” as other elements, and it will be further understood that elements and/or properties thereof recited herein as being “identical” to, “the same” as, or “equal” to other elements may be “identical” to, “the same” as, or “equal” to or “substantially identical” to, “substantially the same” as or “substantially equal” to the other elements and/or properties thereof. Elements and/or properties thereof that are “substantially identical” to, “substantially the same” as or “substantially equal” to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are identical to, the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are identical or substantially identical to and/or the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.
Hereinafter, example embodiments of the present inventive concepts will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present inventive concepts.
Referring to
The wiring structure 110 may have a structure in which at least one insulating layer 111 and at least one wiring layer 112 are alternately stacked. For example, the wiring structure 110 is a support substrate on which the semiconductor chip 120 is mounted, and may be a package substrate for wiring a connection pad 121 of the semiconductor chip 120. The package substrate may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, and the like. The wiring structure 110 may include insulating layers 111, wiring layers 112, wiring vias 113, an upper solder mask layer 115, and a lower solder mask layer 116. In some example embodiments, the number of layers of the insulating layers 111 and the wiring layers 112 forming a wiring structure 110 may be variously changed. In some example embodiments, the wiring structure 110 may be an interposer substrate, for example, an organic interposer. In some example embodiments, the wiring structure 110 may be a module substrate, and in some example embodiments, the semiconductor chip 120 may be a semiconductor structure such as a semiconductor package.
The insulating layers 111 may include an insulating material, and may include, for example, a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. For example, the insulating layers 111 may include a photosensitive insulating material such as a Photoimageable Dielectric (PID) resin. Alternatively or additionally, the insulating layers 111 may include a resin mixed with an inorganic filler, for example, Ajinomoto Build-up Film (ABF). Alternatively or additionally, the insulating layers 111 may include prepreg, flame retardant (FR-4), or bismaleimide triazine (BT). The insulating layers 111 may include the same or different materials. Boundaries between the insulating layers 111 may not be distinguishable depending on (or based on) the materials and processes for forming each layer.
The wiring layers 112 and the wiring vias 113 may form an electrical path. The wiring layers 112 and the wiring vias 113 may wire the semiconductor chip 120 to a region outside the semiconductor chip 120, for example, to a fan-out region, not overlapping the semiconductor chip 120 in a Z-direction. Accordingly, the semiconductor package 100a of some example embodiments may be referred to as a fan-out semiconductor package. However, the form of the semiconductor package is not limited thereto, and in some example embodiments, the semiconductor package 100a may form a fan-in semiconductor package. The wiring layers 112 and the wiring vias 113 may include a ground pattern, a power pattern, and a signal pattern. The wiring layers 112 may be disposed in a line shape on an X-Y plane, and the wiring vias 113 may have a cylindrical shape having a side surface inclined so as to be narrow toward a lower portion or an upper portion thereof. The wiring vias 113 are illustrated as filled vias in which an interior thereof is filled with a conductive material, but example embodiments are not limited thereto. For example, the wiring vias 113 may have a form of conformal vias in which a metal material extends along an inner wall of a via hole.
The wiring layers 112 and wiring vias 113 may include a conductive nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but example embodiments are not limited thereto. Depending on (or based on) a width of wirings of the wiring layers 112 or a gap between the wirings (e.g., 10 μm to 100 μm), the wirings of the wiring layers 112 may be implemented as a redistribution line.
The wiring layers 112 may include a plurality of lower pads 112P3 exposed through a lower solder mask layer 116. The plurality of lower pads 112P3 may be disposed on the lowest insulating layer among the insulating layers 111, and the plurality of lower pads 112P3 may be exposed downwardly through a plurality of upper and lower passages of the lower solder mask layer 116 and electrically connected to the plurality of bumps 160. Each of the plurality of lower pads 112P3 may have a circular or polygonal upper and lower surface. As a diameter d1 of each of the plurality of bumps 160 increases, the width of each of the plurality of lower pads 112P3 may also increase.
The upper and lower solder mask layers 115 and 116 may be solder resist layers protecting the wiring layer 112 from external physical and chemical damage. The upper and lower solder mask layers 115 and 116 may include an insulating material, and may include, for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, BT, or Photo Solder Resist (PSR), but example embodiments are not limited thereto.
The semiconductor chip 120 may be disposed to vertically overlap the wiring structure 110. The semiconductor chip 120 may include connection pads 121 on a lower surface thereof. The semiconductor chip 120 may be mounted on an upper surface of the wiring structure 110 in a flip-chip bonding method. The semiconductor chip 120 may include a device layer or active layer located below the connection pads 121 and on which an integrated circuit (IC) is disposed. The semiconductor chip 120 may include a logic semiconductor chip and/or a memory semiconductor chip. The logic semiconductor chip may be a micro-processor, for example, a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a controller, or an application specific integrated circuit (ASIC), but example embodiments are not limited thereto. The memory semiconductor chip may be a volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), or the like, or a non-volatile memory such as flash memory, or the like, but example embodiments are not limited thereto.
A body portion of the semiconductor chip 120 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, and the connection pads 121 may include a conductive material such as tungsten (W), aluminum (Al), copper (Cu), or the like, but example embodiments are not limited thereto. The connection pads 121 may be pads of a bare chip, for example, aluminum (Al) pads, but according to some example embodiments, the connection pads 121 may be pads of a packaged chip, for example, a copper (Cu) pad. The connection pads 121 may be electrically connected to the wiring layer 112 of the wiring structure 110 through a plurality of chip bumps 130. Being electrically connected may mean providing at least a portion of a path through which signals are transmitted. In some example embodiments, the connection pads 121 may be disposed in the body portion of the semiconductor chip 120 so that a lower surface thereof forms a lower surface of the semiconductor chip 120. In some example embodiments, a passivation layer exposing the connection pads 121 may be further disposed on the lower surface of the semiconductor chip 120. The passivation layer may include a silicon oxide film and/or a silicon nitride film.
The conductive shielding layer 170 may accommodate the semiconductor chip 120, and cover a portion of a side surface (e.g., upper side surface) of the wiring structure 110 to be connected to a ground 112GND of at least one wiring layer 112. In some example embodiments, accepting may mean that the conductive shielding layer 170 surrounds the semiconductor chip 120 and overlaps the semiconductor chip 120 vertically. For example, the conductive shielding layer 170 may have a shape of a cap, and the semiconductor chip 120 may be inserted into an accommodation space of the cap.
Since conductivity of the conductive shielding layer 170 may reflect and/or attenuate electromagnetic noise trying to pass through the conductive shielding layer 170, the conductive shielding layer 170 may electromagnetically shield to reduce the influence of electromagnetic noise outside the semiconductor package 100a on the semiconductor chip 120.
The conductive shielding layer 170 may be connected to a ground 112GND of at least one wiring layer 112, the conductive shielding layer 170 may have electrical stability and further improve electromagnetic shielding performance. For example, a portion of the wiring layers 112 of the wiring structure 110 may be signal/power wirings through which a signal or power flows, and other portions of the wiring layers 112 may be a ground plate and/or ground wiring. The ground plate may surround signal/power wirings. The ground plate and/or ground wiring of the wiring layers 112 may be exposed to a side surface of the wiring structure 110, and the conductive shielding layer 170 may be connected to the ground plate and/or ground wiring of the wiring layers 112 through the side surface of the wiring structure 110.
An edge portion of the conductive shielding layer 170 may be the lowest portion of the conductive shielding layer 170, and may be the most physically vulnerable portion (or may be a physically vulnerable portion) of the conductive shielding layer 170. For example, the conductive shielding layer 170 may be formed by separation or cutting in a wider state, and the separation or cutting may cause physical vulnerability (e.g., burring) in the edge portion of the conductive shielding layer 170. The physical vulnerability (e.g., burring) may be a limiting factor in the reliability of the conductive shielding layer 170. Alternatively or additionally, even without the separation or cutting, if the edge portion of the conductive shielding layer 170 covers a lower corner of the wiring structure 110, the edge portion of the conductive shielding layer 170 itself may become a physical vulnerability.
The other portion of the side surface of the wiring structure 110 (e.g., a lower side surface) may be covered by the conductive shielding layer 170 and exposed. Accordingly, the edge portion of the conductive shielding layer 170 can be prevented from causing physical vulnerability such as a burr (or the likelihood of causing a physical vulnerability such as a burr can be reduced), and the edge of the conductive shielding layer 170 itself may be all prevented from becoming a physical vulnerability (or the likelihood of the edge of the conductive shielding layer 170 itself becoming a physical vulnerability can be reduced). Accordingly, the reliability of the conductive shielding layer 170 can be increased.
For example, the lowermost portion of the conductive shielding layer 170 may be located in an upper level than the lowermost portion of the wiring structure 110. A portion of a side surface of at least one insulating layer 111 (e.g., an insulating layer located on the lower side of the insulating layers or an insulating layer located on the lower side of the wiring layer 112 exposed to the side surface) may not be covered by the conductive shielding layer 170 and exposed. A side surface of the lower solder mask layer 116 may be exposed without being covered by the conductive shielding layer 170.
Since the encapsulant 150 is disposed on an upper side of the wiring structure 110, the conductive shielding layer 170 can completely cover an upper surface and a side surface of the encapsulant 150 (or the conductive shielding layer 170 can cover an upper surface and a side surface of the encapsulant 150). The encapsulant 150 may encapsulate and protect the semiconductor chip 120 on the upper surface of the wiring structure 110. The encapsulant 150 may be disposed to cover side surfaces and an upper surface of the semiconductor chip 120 and may directly contact the side surfaces and upper surface of the semiconductor chip 120, but the present inventive concepts are not limited thereto. The encapsulant 150 may include a molding material such as Epoxy Molding Compound (EMC), but the present inventive concepts are not limited thereto. For example, the encapsulant 150 may include an insulating material, such as a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, an inorganic filler, and/or may also include prepreg containing glass fibers, ABF, FR-4, BT, or PID, but example embodiments are not limited thereto.
A non-conductive film layer 140 may be disposed between the semiconductor chip 120 and the wiring structure 110 to surround the plurality of chip bumps 130. The non-conductive film layer 140 may also be referred to as an underfill layer. The non-conductive film layer 140 may include a non-conductive polymer, for example, a non-conductive paste (NCP). The non-conductive film layer 140 may be formed on the lower surface of the semiconductor chip 120 or the upper surface of the wiring structure 110 during a reflow process or TCB process, and then fill a space between the semiconductor chip 120 and the wiring structure 110. Accordingly, the non-conductive film layer 140 may have a shape that protrudes outwardly of end portions of the semiconductor chip 120. A length at which the non-conductive film layer 140 protrudes horizontally from the side surfaces of the semiconductor chip 120 may be greater at a center thereof in a thickness direction than at the lower surface and the upper surface thereof.
The plurality of bumps 160 may be electrically connected to at least one wiring layer 112 and arranged under at least one insulating layer 111. The plurality of bumps 160 may be electrically connected to at least one wiring layer 112 and arranged under at least one insulating layer 111. The plurality of bumps 160 may physically and/or electrically connect a semiconductor package 100a to an external device such as a main board, or may be electrically connected to an additional semiconductor package below the semiconductor package 100a.
The plurality of bumps 160 may have a larger size and diameter than the plurality of chip bumps 130. Each of the plurality of bumps 160 and the plurality of chip bumps 130 may include a low-melting point (e.g., lower melting point than a melting point of a metal included in the wiring layer 112) metal, such as lead (Pb) or bismuth (Bi), tin (Sn) and an alloy containing tin (Sn) (Sn—Ag—Cu), or the like, but the present inventive concepts are not limited thereto. Each of the plurality of bumps 160 and the plurality of chip bumps 130 may have a land, ball, or pin shape and may be formed of a single layer or multiple layers. For example, the plurality of bumps 160 may be solder balls. At a temperature higher than the melting point, the plurality of bumps 160 and the plurality of chip bumps 130 may have a fluid state by a reflow process or a thermal compression bonding (TCB) process. Thereafter, as the temperature decreases, the plurality of bumps 160 and the plurality of chip bumps 130 may be connected to and fixed to pads of the wiring layer 112.
The semiconductor package 100a may be a high-bandwidth memory (HBM) semiconductor package, and may include a plurality of bumps 160 having a diameter dl longer than each diameter of bumps of other types of semiconductor packages (e.g., AP, NAND). For example, the diameter d1 of each of the plurality of bumps 160 may exceed 200 μm, or may exceed 200 μm and be less than 300 μm (e.g., 250 μm).
As the diameter d1 of each of the plurality of bumps 160 is longer, a degree of freedom in a process of forming the conductive shielding layer 170 may become narrower. For example, as the diameter d1 of each of the plurality of bumps 160 is longer, the efficiency of the process of forming the conductive shielding layer 170 after impregnating the plurality of bumps 160 with an ultraviolet tape may decrease.
Hereinafter, a method of manufacturing a semiconductor package of
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As the plurality of bumps 160 are inserted into the hole 31, an edge of a lower surface of the semiconductor package 100a may directly contact an upper surface of the film 20. For example, the semiconductor package 100a may be disposed on a portion of the upper surface of the film 20 to be immersed in liquid, to be described later. For example, a pick and place device 40 may pick the semiconductor package 100a and move the semiconductor package 100a onto the film 20 and the hole 31.
Referring to
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For example, the liquid 60 may be water containing a surfactant. Accordingly, since a phenomenon in which a portion of the conductive materials 70 floating on a water surface of the liquid 60 may be suppressed, a formation height of the conductive shielding layer 170 may be more accurately adjusted. The specific gravity of water may be 1 and may be lower than the specific gravity of conductive materials (e.g., copper—8, stainless steel—7.8).
Referring to
A structure in which the conductive shielding layer 170 is connected to a ground of the semiconductor package 100a while exposing a lower side surface of the wiring structure of the semiconductor package 100a may require fine control (or may require control) of the formation height of the conductive shielding layer 170. In a method of manufacturing semiconductor packages 100-1, 100-2, 100-3, 100-4a, 100-5a, and 100-6a according to an example embodiment of the present inventive concepts, since the formation height of the conductive shielding layer 170 is finely adjusted (or is adjusted), since the structure in which the conductive shielding layer 170 is connected to a ground of the semiconductor package 100a while exposing a lower side surface of the wiring structure of the semiconductor package 100a may be stably formed (or may be formed), electromagnetic shielding reliability of the semiconductor package 100a may be improved.
Referring to
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Since a formation height of the conductive shielding layer 170 may be adjusted by adjusting a thickness of the coating layer 80, the formation height thereof may be finely adjusted (or may be adjusted). In the method of manufacturing semiconductor packages 100-1, 100-2, 100-3, 100-4b, 100-5b, and 100-6b according to an example embodiment of the present inventive concepts, since the formation height of the conductive shielding layer 170 may be finely adjusted (or may be adjusted), since the structure in which the conductive shielding layer 170 is connected to a ground of the semiconductor package 100a while exposing a lower side surface of the wiring structure of the semiconductor package 100a may be stably formed (or may be formed), electromagnetic shielding reliability of the semiconductor package 100a may be improved.
Referring to
The first conductive shielding layer 171 may directly contact a portion of a side surface of the wiring structure 110. For example, the first conductive shielding layer 171 may directly contact an encapsulant 150, and may include a material (e.g., stainless steel) which is advantageous for being stably disposed (or for being disposed) on a surface of the wiring structure 110 and/or encapsulant 150 and is effective (or beneficial) to be used in a sputtering process.
The second conductive shielding layer 172 may directly contact the first conductive shielding layer 171 and cover the first conductive shielding layer 171. The second conductive shielding layer 172 may include a conductive material (e.g., copper) different from conductive materials (e.g., stainless steel) included in the first and third conductive shielding layers 171 and 173. For example, the material (e.g., copper) of the second conductive shielding layer 172 has high conductivity, so that the material may improve shielding performance, and may be efficiently used in a sputtering process.
The third conductive shielding layer 173 may directly contact the second conductive shielding layer 172 and cover the second conductive shielding layer 172. The third conductive shielding layer 173 may include a material (e.g., stainless steel) having better robustness against an external environment than the second conductive shielding layer 172.
At least according to the semiconductor package manufacturing method of
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The conductive posts 170 may be disposed between the wiring structure 110 and the substrate 180, to electrically connect the wiring structure 110 and the substrate 180. The conductive posts 170 may extend in a vertical direction, for example, a Z-direction, between the wiring structure 110 and the substrate 180, to provide a vertical connection path electrically connecting the wiring layer 112 and the upper wiring layer 182. The conductive posts 170 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy including thereof, and may have a spherical or ball shape extending in the z direction, but example embodiments are not limited thereof.
The substrate 180 is a substrate providing a wiring layer on an upper surface of the first package 100f, and may be disposed between a lower package and an upper package in a Package on Package (POP) structure. The substrate 180 may include upper insulating layers 181, upper wiring layers 182, and wiring vias 183. Since each of the upper insulating layers 181, the upper wiring layers 182, and the wiring vias 183 has the same or similar characteristics as those of the insulating layers 111, the wiring layers 112, and the wiring vias 113 described above, overlapping descriptions are omitted. The uppermost and lowermost upper layers among the upper insulating layers 181 may be a solder mask layer protecting upper interconnection layers 132, and include openings exposing at least a portion of the upper wiring layers 132.
The wiring structure 210 may include upper pads 212 and lower pads 211 exposed through the upper and lower surfaces. The wiring structure 210 may include, for example, silicon (Si), glass, ceramic, or plastic. The wiring structure 210 may include an electrical path 213 formed by wiring patterns therein, and the wiring patterns may have a multi-layer structure.
Additional semiconductor chips 220 may include a logic semiconductor chip and/or a memory semiconductor chip. A device layer is disposed below the additional semiconductor chips 220, so that a lower surface thereof may be active surface, but a dispositional position of the active surface may vary in various example embodiments. The additional semiconductor chips 220 may be mounted on the wiring structure 210 by wire bonding or flip chip bonding. For example, a plurality of additional semiconductor chips 220 may be stacked on the wiring structure 210 in a vertical direction, and electrically connected to an upper pad 212 of the wiring structure 210 by a bonding wire WB. For example, the additional semiconductor chips 220 may include a memory chip, and the semiconductor chip 120 may include an AP chip.
The encapsulant 230 may be disposed to surround the additional semiconductor chips 220, and may serve to protect the additional semiconductor chips 220. The encapsulant 230 may be formed of, for example, a silicone-based material, a thermosetting material, a thermoplastic material, or a UV-treated material, but example embodiments are not limited thereof.
The plurality of bumps 260 may be disposed on a lower surface of the wiring structure 210, and may be connected to at least a portion of the lower pads 211. The plurality of bumps 260 may connect the upper package 200 to a lower package, and thereby, a Package on Package (PoP) structure may be implemented. Since the plurality of bumps 260 may be implemented similarly to the plurality of bumps 160, the plurality of bumps 260 may have a melting point lower than that of the lower pads 211, but the present inventive concepts are not limited thereto.
The conductive shielding layer 270 may accommodate at least one of the additional semiconductor chips 220, cover the encapsulant 230, cover a portion of a side surface of the wiring structure 210, and not cover the other portion of the side surface of the wiring structure 210, which may be exposed.
Referring to
The semiconductor chip 120a of the present example embodiment may have a lower first region CR1 and an upper second region CR2, and may further include device layers 122 and through-vias 125. The first region CR1 may be a device region, and may be a region in which devices such as transistors and/or memory cells forming a semiconductor chip are formed based on the second region CR2. The second region CR2 may be a substrate region and, for example, may be a region including a semiconductor material such as silicon (Si).
The device layers 122 may be disposed in the first region CR1 to comprise the devices. The through-vias 125 may penetrate through the second region CR2 of the semiconductor chip 120a. In some example embodiments, the through-vias 125 may further penetrate through at least a portion of the first region CR1. The through-vias 125 may be electrically connected to the device layers 122 of the first region CR1, and may provide an electrical connection between additional semiconductor chips 220a and the wiring structure 110. The through-vias 125 may be formed of a conductive material, and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).
The additional semiconductor chips 220a may be stacked and disposed on the semiconductor chip 120a in a Z-direction. The additional semiconductor chips 220a may include through-vias 125 except for the uppermost additional semiconductor chip 220a. A first connection region BS1 may be formed between the semiconductor chip 120a and the additional semiconductor chip 220a, and second to fourth connection regions BS2, BS3, and BS4 may be located between the second semiconductor chips 220a, respectively. Although not specifically shown, at least a portion of the first to fourth connection regions BS1, BS2, BS3, and BS4 may have substantially the same structure as that of a connection region between the wiring structure 110 and the semiconductor chip 120a.
For example, in each of the first to fourth connection regions BS1, BS2, BS3, and BS4, the plurality of bumps 260 may be connected between a plurality of second pads 221 of each of the additional semiconductor chips 220a, and may be implemented similarly to the plurality of chip bumps 130, so that the plurality of bumps 260 may have a lower melting point than a melting point of the plurality of second pads 221, but the present inventive concepts are not limited thereto.
The conductive shielding layer 270 may accommodate the semiconductor chip 120a and additional semiconductor chips 220, cover the encapsulant 230, and cover a portion of the side surface of the wiring structure 210, but not cover the other portion of the side surface of the wiring structure 210 and be exposed.
As set forth above, according to an example embodiment of the present inventive concepts, a semiconductor package and a method of manufacturing a semiconductor package may improve electromagnetic shielding reliability.
For example, the semiconductor package and the method of manufacturing a semiconductor package according to an example embodiment of the present inventive concepts may prevent (or reduce the likelihood of having) a separated/cut portion (e.g., edge portion) in a process of forming a structure for electromagnetic shielding (e.g., conductive shielding layer) from becoming physical vulnerability (e.g., burring), so electromagnetic shielding reliability (e.g., durability of the conductive shielding layer or connectivity to ground) can be improved.
While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0137405 | Oct 2023 | KR | national |
