Patent Application
20070252257
The accompanying figures are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain principles of the invention. In the figures:
Preferred embodiments of the invention will be described below in more detail with reference to the accompanying drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, for example, a first layer discussed below could be termed a second layer, and similarly, a second layer may be termed a first layer without departing from the teachings of the present invention. Hereinafter, exemplary embodiments of the present invention will be described in conjunction with the accompanying drawings.
Referring to
The interconnection substrate 100 includes inner input/output terminals 110 for electrically connecting to the semiconductor chip 200, outer input/output terminals 120 for electrically connecting to an external electronic device (not shown), and interconnections (not shown) for connecting the inner and outer input/output terminals 110 and 120. A predetermined adhesive 150 may be disposed between the interconnection substrate 100 and the semiconductor chip 200 to adhere them together.
In order for the semiconductor chip 200 to perform its function, it includes an internal circuit 210 (in
The semiconductor chip 200 includes a bonding pad 240 that is used as an electrically connecting path between the internal circuit 210 and the interconnection substrate 100. In the first embodiment of the invention, a portion of the inner pads 220 may be used as the bonding pads 240. Also, the bonding pads 240 are electrically connected to an inner input/output terminal 110 through wires 250 formed in a wire bonding process.
The heat dissipative element 300 may be one of a heat spreader, a heat sink, a thermal electronic cooler, or a heat pipe, and may be formed of a metal material with favorable thermal conductivity. The heat dissipative element 300 shown in
According to the invention, the heat dissipative element 300 is disposed on the semiconductor chip 200, as described above, uses a predetermined conductive pattern (for example, a redistribution structure described below), and is electrically connected to at least one of the inner pads 220. Accordingly, a conductive path for interconnection is formed between the heat dissipative element 300 and the internal circuit 210, and includes the conductive pattern and the inner pads 220. As a result, the heat generated from the inside of the semiconductor chip 200 (more precisely, the internal circuit 210) can be dissipated much more effectively than in a conventional device lacking this type of conductive connecting path. In more detail, the inner heat energy is dissipated to the outside air through the movements of electrons and the transfer of phonons, and the conductive path for interconnection is helpful as a transfer mechanism of this energy to expedite the transferring process.
To form this conductive path for interconnection, the invention may dispose a redistribution structure between the semiconductor chip 200 and the heat dissipative element 300.
Referring to
The upper lines 410 are electrically connected to at least one of the power pad, ground pad, and signal pads of the semiconductor substrate 200 through the inner pads 220. (Here, the power pad, ground pad, and signal pads are inner pads that supply an electrical voltage, a ground voltage, and a signal voltage, respectively, within the internal circuit 210.) The semiconductor chip 200 may include a plurality of power pads and/or ground pads to supply a stable voltage. In this case, the number of conductive connections between the heat dissipative element 300 and the internal circuit 210 increases, so that inner heat energy can be more effectively dissipated.
The electrical voltage and the ground voltage are statically supplied, so that the upper lines 410 may be connected to the ground pad or the power pad. Also, in order to prevent damage to the semiconductor chip 200 from electrostatic discharge (ESD), the internal circuit 210 may include an ESD prevention circuit connected to the inner pads 220, which are connected to the upper lines 410. The ESD prevention circuit may be a conventional ESD prevention circuit, and may be disposed between the inner pads 220 and the microelectronic devices in the internal circuit 210.
The upper lines 410 may be connected to at least two of the power pad, ground pad, and signal pads. In this case, in order to prevent a short, the heat dissipative element 300 may be formed in two divided parts, which are respectively connected to different inner pads 220, as shown in
When the upper bumps 420 are disposed above the upper lines 410, a plurality of upper bumps 420 may be disposed above one upper line 410. Thus, the resistance between the heat dissipative element 300 and the upper lines 410 decreases, and the adhesion therebetween increases. The redistribution structure may be formed using conventional methods (for example, the method disclosed in Korean Patent No. 2003-0050496, which is hereby incorporated by reference in its entirety).
Referring to
The first and second semiconductor chips 201 and 202 and the package structure in the form of the interconnection substrate 100 may use a conventional packaging technology. For example, the first and second semiconductor chips 201 and 202 according to this embodiment may use conventional package structures with a plurality of semiconductor chips (such as those disclosed in U.S. Pat. No. 6,869,827, U.S. Pat. No. 6,680,212, and Japanese Patent No. 2001-015679, which are hereby incorporated by reference in their entirety), to become a package for the interconnection substrate 100.
According to this embodiment, an upper semiconductor chip (that is, the second semiconductor chip 202) may include the redistribution structure described above, and the heat dissipative element 300 is attached at the top thereof. As described, the heat dissipative element 300 is electrically connected to the second semiconductor chip 202 through the redistribution structure. As a result, heat generated from the upper semiconductor chip 202 can easily be dissipated to the outside air.
According to this embodiment, the heat dissipative element 300 may be disposed to enclose the sidewalls of the first and second semiconductor chips 201 and 202. In this case, the heat dissipative element 300 may be electrically separated from the inner input/output terminals 110 of the interconnection substrate 100, to prevent a short. It is apparent that the first semiconductor chip 201 directly attached to the interconnection substrate 100 is better able to dissipate heat from inside than the second semiconductor chip 202. Thus, a package structure that can effectively dissipate heat from the second semiconductor chip 202 is required, a requirement that the heat dissipative element 300 fulfills.
Referring to
Then, referring to
Referring to
Referring to
The internal circuit of a semiconductor chip according to the invention is electrically connected to a heat dissipative element that is exposed to outside air through predetermined conductive patterns (for example, a redistribution structure). Therefore, the heat generated by the semiconductor chip can effectively be dissipated to the outside air.
Embodiments of the invention provide a semiconductor package structure having a heat dissipative element directly connected to the internal circuit of the semiconductor chip. The semiconductor package includes: a semiconductor chip including an internal circuit and inner pads connected to the internal circuit; an interconnection substrate disposed below the semiconductor chip and including input/output terminals; at least one wire for connecting at least one of the inner pads to the input/output terminals; and a heat dissipative element disposed on the semiconductor chip and electrically connected to at least one of the inner pads.
In some embodiments, the semiconductor package may further include a redistribution structure disposed between the heat dissipative element and the semiconductor chip, for connecting the heat dissipative element and the inner pads. The inner pads may include a power pad for connecting a power voltage, a ground pad for connecting a ground voltage, and a plurality of signal pads for connecting signal voltages; and the redistribution structure may include upper lines disposed on the semiconductor chip and connected to the internal circuit through the inner pads, and at least one upper bump disposed on at least one of the upper lines and connecting the inner pads.
In other embodiments, the redistribution structure may further include at least one bonding pad for bonding to the wire, and the at least one bonding pad may be disposed on an upper surface perimeter of the semiconductor chip and may be electrically connected to the inner pads through the upper lines. The signal pads may be disposed on an upper surface perimeter of the semiconductor chip, and the wire may be bonded to the signal pads.
In still other embodiments, the heat dissipative element may be connected to the ground pad through the redistribution structure. Also, the heat dissipative element may be connected to the power pad through the redistribution structure. Further, the heat dissipative element may be connected to at least one of the signal pads through the redistribution structure. The heat dissipative element may be at least one of a heat spreader, a heat sink, a thermal electronic cooler, a heat pipe, and a conductive layer with high thermal conductivity.
In even other embodiments, the heat dissipative element may be separated from at least one of the input/output terminals and may cover top and side surfaces of the semiconductor chip. The heat dissipative element may be electrically connected to the internal circuit through one of the inner pads and exposed to outside air, for dissipating heat generated by the internal circuit of the semiconductor chip to the outside air through electron movement.
In yet other embodiments, the internal circuit may include: microelectronic devices including a semiconductor device, a resistor, and a capacitor; an inner interconnection structure electrically connecting the microelectronic devices to the inner pads; and at least one ESD (electrostatic discharge) preventing circuit, wherein the ESD preventing circuit may be disposed between the inner pads to which the heat dissipative element is connected and the microelectronic devices.
In further embodiments, the interconnection substrate may include: external input/output terminals for transmitting signals to and from an external electronic device; lines connecting the input/output terminals to the external input/output terminals; and lower bumps disposed below the external input/output terminals.
In other embodiments of the invention, methods for packaging a semiconductor chip for directly connecting an internal circuit of the semiconductor chip to a heat dissipative element are provided. The methods include: manufacturing a semiconductor chip including an internal circuit and inner pads connected to the internal circuit; performing a redistribution process for forming a redistribution structure including bonding pads connected to the inner pads; attaching the semiconductor chip with the redistribution structure formed thereon on an interconnection substrate including input/output terminals; connecting the bonding pads to the input/output terminals using a wire; and attaching a heat dissipative element electrically connected to the internal circuit through the redistribution structure and the inner pads on the redistribution structure.
In still other embodiments the forming of the redistribution structure may include: forming upper lines connected to the inner pads; and forming upper bumps on the upper lines. The method may further include: forming a protective layer covering the wire; and etching the protective layer and exposing the upper bumps, prior to the attaching of the heat dissipative element, wherein the attaching of the heat dissipative element includes electrically connecting the exposed upper bumps and the heat dissipative element. The method may further include filling a gap between the heat dissipative element and the interconnection substrate with a protective layer, after the attaching of the heat dissipative element.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the invention. Thus, to the maximum extent allowed by law, the scope of the invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0038204 | Apr 2006 | KR | national |
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2006-0038204, filed on Apr. 27, 2006, the entire contents of which are hereby incorporated by reference.
