Patent Application
20240120282
The present disclosure relates to a semiconductor structure, and more particularly, to a semiconductor structure having a die-stacking structure.
To gain greater computation capability in a smaller area with lower power consumption, a die-stacking technology has been developed and adopted in semiconductor packaging processes. However, routing of traces between dies and external pads has become complicated since the traces need to be arranged densely within a limited area when the dies are stacked. Furthermore, to protect data signals and/or control signals from interference by power signals, certain rules must be followed when routing the traces, which makes the trace routing even more difficult. Therefore, providing a semiconductor structure that can facilitate the trace routing has become an issue to be solved.
One embodiment of the present disclosure discloses a semiconductor structure. The semiconductor structure includes a backside redistribution layer (RDL), a plurality of bumps, a dielectric layer, a plurality of through dielectric vias (TDVs), a plurality of first dies, and a second die. The plurality of bumps are disposed on a first surface of the backside RDL, and the dielectric layer is disposed on a second surface of the backside RDL. The plurality of TDVs pass through the dielectric layer. The plurality of first dies are disposed within the dielectric layer, and each of the plurality of first dies includes a first substrate, a plurality of through silicon vias (TSVs), a first device layer and a first RDL. The first substrate is disposed on the backside RDL, and the plurality of TSVs pass through the first substrate and contact conductive paths in the backside RDL. The first device layer is disposed on the first substrate, and the first RDL is disposed on the first device layer. The second die is stacked on the plurality of first dies in a face-to-face manner, and the second die includes a second substrate, a second device layer, and a second RDL. The second device layer is disposed on the second substrate, and the second RDL is disposed on the second device layer. The second RDL is coupled to the first RDL and the plurality of TDVs. Each of the plurality of first dies receives a first supply voltage through at least one first bump of the plurality of bumps, at least one first conductive path in the backside RDL, and at least one TSV of the plurality of TSVs. The second die receives a second supply voltage through at least one second bump of the plurality of bumps, at least one second conductive path in the backside RDL, and at least one TDV of the plurality of TDVs.
Another embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure. The method includes obtaining a plurality of first dies, wherein each of the plurality of first dies comprises a first substrate, a first device layer disposed on the first substrate, and a first redistribution layer (RDL) disposed on the first device layer; forming a second device layer of a second die on a second substrate of the second die; forming a second RDL of the second die on the second device layer; stacking the plurality of first dies on the second die in a face-to-face manner; planarizing first substrates of the plurality of first dies; forming a dielectric layer on the second die, wherein the dielectric layer covers the plurality of first dies; removing a part of the dielectric layer to expose the first substrates of the plurality of first dies; forming a plurality of TDVs in the dielectric layer; forming a plurality of TSVs in the first substrates of the plurality of first dies; forming a backside RDL on the dielectric layer and the plurality of first dies, wherein the backside RDL is coupled to the plurality of TDVs and the plurality of TSVs; and forming a plurality of bumps on the backside RDL.
Another embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure. The method includes obtaining a plurality of first dies, wherein each of the plurality of first dies comprises a first substrate, a first device layer disposed on the first substrate, and a first redistribution layer (RDL) disposed on the first device layer; forming a second device layer of a second die on a second substrate of the second die; forming a second RDL of the second die on the second device layer; forming a plurality of copper pillars on the second RDL; stacking the plurality of first dies on the second die in a face-to-face manner; planarizing first substrates of the plurality of first dies; forming a dielectric layer on the second die, wherein the dielectric layer covers the plurality of first dies and the plurality of copper pillars; removing a part of the dielectric layer to expose the first substrates of the plurality of first dies and the plurality of copper pillars; forming a plurality of through silicon vias (TSVs) in the first substrates of the plurality of first dies; forming a backside RDL on the dielectric layer and the plurality of first dies, wherein the backside RDL is coupled to a plurality of TDVs formed by the plurality of copper pillars and the plurality of TSVs; and forming a plurality of bumps on the backside RDL.
Since the semiconductor structure and the methods for manufacturing the semiconductor structure allow backside power delivery in die-stacking structures, more space can be provided for trace routing between stacked dies. As a result, greater computation power can be achieved within a smaller chip area with less power loss.
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures.
The following description accompanies drawings, which are incorporated in and constitute a part of this specification, and which illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. Preferred embodiments of the present disclosure will be described in detail below. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.
As shown in
In the present embodiment, the semiconductor structure 100 allows backside power deliveries for the first dies 150. For example, the first dies 150 can receive supply voltages through TSVs 154 formed in backside substrates 152 of the first dies 150. Also, the second die 160 may receive supply voltages through the TDVs 140 formed in the dielectric layer 130. In such case, power supply paths for the second die 160 don't need to pass through the first dies 150. Therefore, the region where the first dies 150 overlaps the second die 160 from a top view is unnecessary to accommodate power supply paths of the second die 160. In other words, the overlap region of the first dies 150 and the second die 160 can be more efficiently used for the transmission lines of control signals and/or data signals, thereby allowing better flexibility of trace routing.
In the present embodiment, the first dies 150 can be chiplet core dies, which include computation circuits 170, while the second die 160 can be a memory die, which includes a memory circuit 180. The memory circuit 180 can, for example, be a cache memory of the computation circuits 170. The memory circuit 180 may be a static random-access memory (SRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM) and/or another type of memory. In such case, the computation circuits 170 in the first dies 150 can access the memory circuit 180 of the second die 160 through vertical transmission between dies, thereby allowing fast data sharing among different cores. However, the present disclosure is not limited thereto. In some other embodiments, the first dies 150 and the second die 160 may include other types of circuits according to different design needs.
For example, as shown in
Furthermore, in the present embodiment, die sizes of the first dies 150 can be smaller than a die size of the second die 160. Generally, since configurations inside the first dies 150 can be rather complicated, manufacturing the first dies 150 with smaller die sizes can be beneficial in terms of increasing yield rates. However, in the memory circuit 180, since defective cells can be easily replaced with other good cells as needed, the yield rate of the second die 160 is usually not an issue. Therefore, the second die 160 can be manufactured with a greater die size to increase memory capacity. Furthermore, since the semiconductor structure 100 allows fast signal transmission with the traces formed between the first dies 150 and the second die 160, it is feasible to form the input/output circuits 190 of the computation circuits 170 in the second die 160, and allows the computation circuits 170 to communicate with the input/output circuits 190 through the vertical traces formed between the first dies 150 and the second die 160. As a result, the die size of the first dies 150 can be further reduced, and the yield rate of the first dies 150 can be further improved.
As shown in
The second die 160 can be stacked on the first dies 150. The second die 160 includes a substrate 162, a device layer 164 disposed on the substrate 162, and an RDL 166 disposed on the device layer 164. In the present embodiment, the memory circuit 180 and the input/output circuits 190 can be formed in the device layer 164 and the RDL 166 of the second die 160. Furthermore, the RDL 166 of the second die 160 can be coupled to the RDLs 158 of the first dies 150 and the TDVs 140. That is, the second die 160 can be stacked on the first die 150 in a face-to-face manner. In some embodiments, the RDL 166 of the second die 160 can be coupled to the RDL 158 of the first dies 150 using hybrid bonding. In such case, the data signals and/or the control signals can be transmitted between the computation circuit 170 and the memory circuit 180 through vertical paths provided by the RDLs 158 and 166 and hybrid bonds between the RDLs 158 and 166. In a conventional 2.5D package, multiple dies may be disposed on a package substrate side-by-side, and the signal transmission among different dies must pass through the traces provided by the packaging substrate to Comparing to such conventional structure, the stacking structure of the semiconductor structure 100 can shorten the signal transmission paths between dies, thereby increasing memory access speed.
Furthermore, in the present embodiment, the first dies 150 may include power terminals, and the power terminals can receive supply voltages through the bumps 120, the conductive paths in the backside RDL 110, and the TSVs 154, for example, paths P7 and P8 shown in
In addition, the second die 160 may include power terminals that can receive supply voltages through the bumps 120, the conductive paths in the backside RDL, and the TDVs 140, for example, paths P9 and P10 shown in
In some embodiments, the semiconductor structure 100 can be deemed as a system on chip (SoC) and can be packaged with high bandwidth memories (HBMs) as a semiconductor chiplet to provide a more complete solution within a smaller size, as shown in
In the present embodiment, the semiconductor structure 200 includes six first dies 250 and a second die 260. In addition, each of the six HBMs 22 can be coupled to a computation circuit of a corresponding first die 250 of the six first dies. However, the present disclosure is not limited thereto. In some embodiments, the semiconductor structure 200 may include a greater or smaller number of first dies 250. Furthermore, in some embodiments, the semiconductor chiplet 20 may include more semiconductor structures 200 if a size of the interposer 24 is sufficient.
In some embodiments, while the computation circuits are formed in the first dies 350 (or 250), the physical interface circuits (PHY) of the computation circuits for interfacing with the HBMs 32 (or 22) can be disposed in the second die 360 (or 260). Similarly, serializer/deserializers (SerDes) for serial high-speed analog data transmission and reception can also be disposed in the second die 360 (or 260), thereby reducing die sizes of the first dies 350 (or 250). In such case, the computation circuits in the first dies 350 (or 250) can be coupled to the physical interface circuits and the serializer/deserializers through RDLs of the first dies 350 (or 250) and the second die 360 (or 260) and hybrid bonds between the RDLs.
In step S102, first dies 150 are obtained, wherein each of the first dies 150 includes a substrate 152, a device layer 156 disposed on the substrate 152, and an RDL 158 disposed on the device layer 156 as shown in
In steps S104 and S106, a device layer 164 and an RDL 166 of the second die 160 are formed sequentially as shown in
After the first dies 150 are stacked on the second die 160, a grinding process may be performed to planarize substrates 152 of the first dies 150 in step S110 as shown in
In step S112, a dielectric layer 130 can be formed on the second die 160 to cover the first dies 150 as shown in
In step S114, a part of the dielectric layer 130 can be removed so as to expose the first substrates 152 of the first dies 150. In the present embodiment, the first dies 150 may further include stop layers 153 formed in the substrates 152 as shown in
Next, in step S116, TDVs 140 can be formed in the dielectric layer 130 as shown in
In sub-step S1161, openings 132 in the dielectric layer 130 can be formed as shown in
In sub-step S1163, the copper layer 142 is polished to the stop layers 153 of the first dies 150, and the TDVs 140 can be formed as shown in
After the TDVs 140 are formed, TSVs 154 can be formed in the substrate 152 in step S118 as shown in
In step S120, a backside RDL 110 can be formed on the dielectric layer 130 and the first dies 150. As shown in
After the backside RDL 110 is formed, bumps 120 can be formed on a first surface of the backside RDL 110 in step S122 as shown in
In the present embodiment, steps S104 to S122 can be performed during a wafer process of the second die 160; therefore, after the semiconductor structure 100 is formed on the wafer, the method M1 may further include placing the wafer, in which the second die 160 is formed, on a dicing tape so as to frame the second die 160. In such case, the second die 160 can be diced from the wafer along with the first dies 150, the backside RDL, and the bumps 120. Thus, the semiconductor structure 100 can be obtained.
In the method M1, the first dies 150 can be stacked on the second die 160 before the TDVs 140 are formed; however, the present disclosure is not limited thereto. In some other embodiments, the TDVs 140 can be formed before the first dies 150 are stacked on the second die 160. In such case, the step for patterning the dielectric layer 130 may be skipped, thereby simplifying the manufacturing process of the semiconductor structure 100.
In the present embodiment, steps S202 to S206 are same as steps S102 to S106, and are shown in
After the first dies 150 are stacked on the second die 160, a grinding process may be performed to planarize the substrates 152 of the first dies 150 in step S212 as shown in
In step S214, the dielectric layer 130 can be formed on the second die 160 to cover the first dies 150 and the copper pillars 144 as shown in
In the present embodiment, the first dies 150 may further include stop layers 153 formed in the substrates 152. In such case, the step S216 may include two grinding and etching processes. The first grinding and etching process can be stopped when reaching the stop layers 153, and the second grinding and etching (or planarization) process, such as a chemical-mechanical polishing (CMP) process, may be performed to make the substrate 152 even thinner and remove the stop layers 153. After the stop layers 153 are removed, the TSVs 154 can be formed in step S218 as shown in
In step S220, the backside RDL 110 can be formed on the dielectric layer 130 and the first dies 150 as shown in
In summary, the semiconductor structure and methods for manufacturing the semiconductor structures provided by the embodiments of present disclosure allow backside power delivery in die-stacking structures. Since the bottom dies, that is, the first dies on which the second die is stacked, can receive power supplies from the tiny TSVs formed in the backside substrates, more space can be provided for trace routing between the stacked dies. As a result, greater computation capability can be achieved within a smaller chip area with less power loss.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.
This application claims the benefit of prior-filed U.S. provisional application No. 63/378,697, filed on Oct. 7, 2022, which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63378697 | Oct 2022 | US |
