Patent Application
20120182651
Conventional electronic systems for computation, communication, and other applications are typically built up from integrated circuits (ICs) arranged in packages or chips and connected to power supplies, circuit elements and other ICs in separate packages or ICs by way of wiring traces on printed circuit boards. Each IC requires connections through the package for power and electrical ground returns, as well as other package connections, which can include both low-rate control signals and high-rate data signals.
Relatively faster ICs include smaller traces and circuit elements. As IC traces and elements become smaller, electrostatic discharge protection increases in importance. An electrostatic discharge is a rapid transfer of electrostatic charge between two objects at different electrostatic potentials. Direct contact, or even bringing the objects in close proximity to each other, can induce such a charge transfer. When the receiving object is an IC or an IC assembly, internal traces and circuit elements can be damaged rendering the IC inoperable or significantly decreasing the useful life of a device made with the damaged IC or ICs.
Electrical connections for the transfer of signals to and from the IC or IC assembly have been protected from ESD by on-chip circuits connected to the chip's terminals (input/output pads) for this purpose. These circuits prevent damage due to ESD events while handling, packaging, shipping, testing, and final assembly. Such protective circuits typically use diodes or silicon-controlled rectifiers coupled to each signal connection to protect the I/O circuits on the IC. Such circuits have proved effective at controlling ESD damage, but they require a significant amount of area and add capacitance to input/output terminals, decreasing performance and increasing power consumption.
The rate of increases in on-circuit density and operating frequency of high-performance ICs have exceeded the rate of increase in interconnections available between packages and printed circuit boards. One method to provide increased communication bandwidth between integrated circuits involves directly bonding one circuit to another, rather than placing each IC in separate packages subsequently connected through traces of a printed circuit board. Such a chip-to-chip bonding approach could effect both the structural and electrical connection between chips by bonding copper terminals of various interconnect lines on the printed circuits together, for example by direct copper fusion bonding, or through patterned solder connections.
Direct chip-to-chip bonding enables area arrays of chip-to-chip interconnections. The area required for definition of a copper stud contact point for direct chip-to-chip attachment is potentially very small, for example down to a few square microns, or eventually even less than one square micron. Such small connections tend to have correspondingly lower parasitic capacitance compared to conventional chip-to-chip interconnections through packages and printed circuit board traces. Because both the required area and the parasitic capacitance are significantly reduced with direct chip-to-chip connections, the overhead penalties in chip area and performance for the addition of ESD protection devices at each terminal are proportionally larger than for conventional interconnections. An objective in direct chip-to-chip bonding is to make high-speed chip-to-chip connections approach within-chip connections in terms of density and performance. To achieve this objective, a method is needed to provide ESD protection for such high-speed bonded chip-to-chip connections without the corresponding area and performance overhead of conventional ESD protection techniques.
An embodiment of a method for protecting I/O circuits on an IC from ESD includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one conductive stud to the at least one protective device.
An embodiment of an IC assembly includes first and second semiconductor dice. A first semiconductor die has a first surface and opposed surface. The first surface includes at least one protective device within a conductive shorting layer in a select region above the first surface. The conductive shorting layer electrically couples at least one conductive element (e.g., a metallic stud) to the at least one protective device. The second semiconductor die has at least one respective conductive element that when arranged in registration to and coupled with the first semiconductor die completes a circuit between the first semiconductor die and the second semiconductor die.
The figures and detailed description that follow are not exhaustive. The disclosed embodiments are illustrated and described to enable one of ordinary skill to use conductive shorting layer patterning to wafer test an IC or functionally test I/O connections and power connections in a core region of an IC assembly, while ESD protecting I/O circuits and circuit elements more susceptible to damage from ESD events. Other embodiments, features and advantages will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional embodiments, features and advantages are within the scope of the assemblies and methods for the manufacture thereof as defined in the accompanying claims.
The IC, IC assembly and methods for protecting I/O circuits on such devices from ESD can be better understood with reference to the following figures. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of electrically coupling I/O circuits to a protective device. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.
The invention provides means for dense arrays of high-speed chip-to-chip bonded interconnections to be protected from ESD during handling and assembly (bonding) without area or performance penalty due to ESD protection. This result is achieved by electrically connecting a large number of chip-to-chip bonding terminals to a single remote on-chip ESD protection device before and during chip-to-chip bonding, and then physically severing the connection between the terminals and the ESD device after bonding is completed. The shorting together of the many high-speed interface terminals with the ESD device is accomplished through a thin film metal layer exposed on the chip surface, so that the shorting film is accessible for removal after chip-to-chip bonding.
The shorting layer might be efficiently implemented as a seed layer which is commonly used to initiate plating of the metal (typically copper) forming the bonding terminals. The shorting layer would be patterned to short together sets of high speed input/output terminals to their associated ESD protection devices, while leaving the power supply terminals and low-speed control and test port terminals available for test prior to assembly. (Power supply and other terminals not connected by the shorting layer could be conventionally ESD protected.)
The shorting layer can be physically removed by etching after the chip-to-chip bonding is completed. Such etching could be aqueous (e.g., hydrogen peroxide for removal of a tungsten shorting layer), or it could be performed by dry etching (e.g., xenon-difluoride etching of a conductive amorphous silicon layer). Additional testing of the coupled semiconductor dice may be performed after bonding and before removal of the shorting layer. Alternatively, additional testing of the coupled semiconductor dice can be performed after removal of the shorting layer.
An electrically conductive shorting layer is applied over a select region of a semiconductor die to couple relatively high-speed I/O connections to an ESD protection device. An IC arranged with such a conductive shorting layer enables wafer level testing of connections that are electrically isolated from an electrical ground or ESD protective device, while protecting other, I/O circuits from potential damage due to ESD events. Wafer level tested connections may include serial signal ports and power connections. The die can be electrically and physically coupled to a second semiconductor die (or to multiple die) to form an IC assembly. When the high-speed I/O connections are formed by metallic studs extended by metal layers and/or conductive spacers, the IC assembly can be fusion bonded along opposed surfaces of the metal layers.
Multiple ESD protection devices, in contact with the shorting layer, can be arranged near opposed corners of a semiconductor die. Alternatively, ESD protection devices can be arranged along or near opposed sides of the semiconductor die.
Location of the shorting layer along the perimeter of the IC assembly improves access to the shorting layer of the respective semiconductor dice for post-bond removal. While a perimeter arrangement of the high-speed connections may be desired for fusion bonded IC assemblies consisting of two similarly sized semiconductor dice, a perimeter arrangement of the high-speed connections is natural for fusion bonded IC assemblies consisting of a primary die with one or more smaller overlapping bridge dice connecting a neighboring primary die. However, it should be understood that high-speed connections protected by the shorting layer need not be exclusively located at or proximal to the die perimeter.
The shorting layer or shorting layers can be removed via exposure to a liquid or gas in an etching process. Upon completion of wafer testing of connections electrically isolated from the conductive shorting layer followed by die bonding, the electrically conductive shorting layer or shorting layers (from the respective dice) are removed to electrically isolate and thereby enable the relatively high-speed I/O connections between the first semiconductor die and the second semiconductor die.
Turning now to the drawings, wherein like reference numerals designate corresponding parts throughout the drawings, reference is made to
The second or select region 120 includes at least one ESD protective device 122 and metallic studs 125. The ESD protective device 122 is electrically coupled to each of the metallic studs 125 by an electrically conductive shorting layer. The shorting layer is formed from tungsten, titanium, or a compound of tungsten and titanium deposited or otherwise applied along the active surface of the semiconductor die 100 above the select region 120. In an alternative embodiment, the shorting layer may be formed of a conductive polysilicon. The conductive polysilicon can be controllably removed by a gaseous etching agent (e.g., a gas including a compound of xenon diflouride). The core region 110 is masked or otherwise protected while the shorting layer is formed on the semiconductor die 100, or the shorting layer could be deposited across the entire die and removed from the core region 110 while protected in the select region 120.
In the example embodiment, the select region 120 entirely surrounds the core region 110. The select region 120 is not limited to the illustrated arrangement. For example, the select region 120 may be arranged along one or more edges of the semiconductor die 100. When the select region 120 is arranged along two edges of the semiconductor die 100, the select region 120 may include adjacent edges or opposed edges of the semiconductor die 100. However arranged, the select region 120 is wide enough to electrically couple the ESD protective device 122 to each of the metallic studs 125. In the example embodiment, the select region 120 is substantially wider than the ESD protective device 122 and the metallic studs 125. However, the select region 120 is not so limited and can be arranged in other widths or shapes that do not entirely encompass but still contact at least some portion of an ESD protective device 122 and the metallic studs 125.
An ESD protective device 122 is any circuit or arrangement of circuits and circuit elements intended to divert potentially damaging electrostatic charge transfers away from sensitive circuitry, such as circuitry coupled to respective metallic studs 125. In the example embodiment, the semiconductor die 100 is arranged with ESD protective devices 122a-122d near each corner of the die. A first ESD protective device 122a is located near a first corner. A second ESD protective device 122d is located near a second corner opposed to the first corner and the first ESD protective device 122a. A third ESD protective device 122b and fourth ESD protective device 122c are located near respective corners of the semiconductor die 100. As shown in
The metallic studs 125 extend above the upper surface of the semiconductor die 100 along an axis orthogonal to both the Y-axis and the X-axis. The metallic studs 125 are coupled to one or more ICs or circuit elements that support relatively high-speed I/O connections when the semiconductor die 100 is arranged in a die-to-die IC assembly with a second similarly configured semiconductor die. For illustrative purposes, only a single semiconductor die is presented in
In an alternative arrangement, the respective contact surfaces 320 may be physically and electrically coupled to each other with solder (not shown). In still another alternative arrangement, additional conductive spacers (not shown) can be added to one or both of the contact surfaces 320 of the respective semiconductor die 100 to provide access to the power and serial test connections located within the core region 110 of the assembly 400. The additional conductive spacers can be fusion bonded and/or soldered to the respective metal layers 316 on the semiconductor dice 100. The conductive spacers used to connect terminals in the core region 110 of one die to another might consist of plated pillars such as those described for the connections in the select region 120, which might be formed during the same process steps described in
ESD protection is provided by the electrical coupling of the shorting layer 304 to the one or more ESD protective devices 122 (
While various example embodiments of ICs, IC assemblies and methods for protecting I/O circuits on an IC from ESD have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible that are within the scope of this disclosure. Accordingly, the described IC assemblies and methods for protecting circuits therein from ESD events are not to be restricted or otherwise limited except in light of the attached claims and their equivalents.
