Stacked semiconductor device

Abstract

A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic cross sectional view showing a structure of a stacked semiconductor device according to a preferred first embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram showing only a power supply portion of the stacked semiconductor device shown in FIG. 1;

FIG. 3 is a schematic cross sectional view showing a structure of a stacked semiconductor device according to a preferred second embodiment of the present invention;

FIG. 4 is an equivalent circuit diagram showing only a power supply portion of the stacked semiconductor device shown in FIG. 3;

FIG. 5 is a schematic cross sectional view showing a structure of a stacked semiconductor device according to a preferred third embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram showing only a power supply portion of the stacked semiconductor device shown in FIG. 5;

FIG. 7 is a schematic cross sectional view showing a structure of a conventional stacked semiconductor device; and

FIG. 8 is an equivalent circuit diagram showing only a power source portion of the stacked semiconductor device shown in FIG. 7.

Claims

1. A stacked semiconductor device in which a plurality of semiconductor chips including at least first and second semiconductor chips are stacked, comprising: an external power supply terminal;a first connection means that electrically connects a power supply wiring arranged in the first semiconductor chip and the external power supply terminal;a second connection means that electrically connects a power supply wiring arranged in the second semiconductor chip and the external power supply terminal; anda third connection means that mutually electrically connects the power supply wirings each provided in adjacent semiconductor chips.

2. The stacked semiconductor device as claimed in claim 1, wherein the third connection means includes a through electrode arranged in the plurality of semiconductor chips.

3. The stacked semiconductor device as claimed in claim 1, further comprising an interposer substrate on which the external power supply terminal is arranged, wherein the plurality of semiconductor chips are stacked on the interposer substrate.

4. The stacked semiconductor device as claimed in claim 3, wherein the first semiconductor chip is a semiconductor chip nearest to the interposer substrate.

5. The stacked semiconductor device as claimed in claim 4, wherein the first connection means includes a bump electrode that electrically connects the power supply wiring arranged in the first semiconductor chip and a power supply wiring arranged in the interposer substrate.

6. The stacked semiconductor device as claimed in claim 3, wherein the second semiconductor chip is a semiconductor chip farthest from the interposer substrate.

7. The stacked semiconductor device as claimed in claim 6, wherein the second connection means includes a bypass conductor that electrically connects the power supply wiring arranged in the second semiconductor chip and a power supply wiring arranged in the interposer substrate.

8. The stacked semiconductor device as claimed in claim 7, wherein a plurality of the bypass conductors are arranged in parallel.

9. The stacked semiconductor device as claimed in claim 6, further comprising a cap substrate arranged opposite, seen from the second semiconductor chip, to the interposer substrate, wherein the second connection means electrically connects the external power supply terminal and the power supply wiring that is arranged in the second semiconductor chip, via the power supply wiring arranged in the cap substrate.

10. The stacked semiconductor device as claimed in claim 9, further comprising an underfill material that is arranged between the interposer substrate and the cap substrate, and covers the plurality of semiconductor chips.

11. The stacked semiconductor device as claimed in claim 1, wherein the plurality of semiconductor chips further include a third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip, anda power supply wiring of the third semiconductor chip is electrically connected to the power supply wirings of the first and the second semiconductor chips by the third connection means, and is electrically connected in a bypassing manner to the external power supply terminal by a fourth connection means different from the third connection means.

12. The stacked semiconductor device as claimed in claim 3, wherein the plurality of semiconductor chips further include a third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip, anda power supply wiring of the third semiconductor chip is electrically connected to the power supply wirings of the first and the second semiconductor chips by the third connection means, and is electrically connected in a bypassing manner to the external power supply terminal by a fourth connection means different from the third connection means.

13. The stacked semiconductor device as claimed in claim 12, further comprising an intermediate interposer substrate arranged between the first semiconductor chip and the second semiconductor chip, wherein the power supply wiring arranged in the third semiconductor chip and a power supply wiring arranged on the intermediate interposer substrate are electrically connected by a bump electrode, andthe fourth connection means includes a bypass conductor that electrically connects the power supply wiring arranged on the interposer substrate and the power supply wiring arranged on the intermediate interposer substrate.

14. The stacked semiconductor device as claimed in claim 7, wherein the bypass conductor is a bonding wire.

15. A stacked semiconductor device, comprising: a plurality of stacked semiconductor chips; anda power supply wiring that supplies a power supply potential to the plurality of semiconductor chips, whereinthe power supply wiring has a loop structure that includes a portion that goes through a through electrode arranged in the plurality of semiconductor chips, and a portion that goes through at least one bypass conductor.

16. The stacked semiconductor device as claimed in claim 15, further comprising an interposer substrate on which the plurality of semiconductor chips are mounted, wherein one end of the at least one bypass conductor is connected to the interposer substrate, and the other end of the at least one bypass conductor is connected to one of the plurality of semiconductor chips that is arranged in a top layer.

17. The stacked semiconductor device as claimed in claim 15, wherein the plurality of semiconductor chips include at least a first semiconductor chip group and a second semiconductor chip group,the at least one bypass conductor includes first and second bypass conductors, andthe loop structure of the power supply wiring includes a first loop structure including a portion that goes through a through electrode arranged in the first semiconductor chip group and a portion that goes through the first bypass conductor; and a second loop structure including a portion that goes through a through electrode arranged in the second semiconductor chip group and a portion that goes through the first and the second bypass conductors.

18. The stacked semiconductor device as claimed in claim 17, further comprising an intermediate interposer substrate arranged between the first semiconductor chip group and the second semiconductor chip group, wherein one end of the first bypass conductor is connected to the interposer substrate and the other end of the first bypass conductor is connected to the intermediate interposer substrate, andone end of the second bypass conductor is connected to the interposer substrate and the other end of the second bypass conductor is connected directly or indirectly to a semiconductor chip that is arranged in a top layer and included in the second semiconductor chip group.

19. A stacked semiconductor device, comprising: a plurality of stacked semiconductor chips;means for supplying a power supply potential in a cascade manner to the plurality of semiconductor chips from a side of a bottom-layered semiconductor chip among the plurality of semiconductor chips; andmeans for supplying a power supply potential in a cascade manner to the plurality of semiconductor chips from a side of a top-layered semiconductor chip among the plurality of semiconductor chips.

20. The stacked semiconductor device as claimed in claim 19, further comprising means for supplying a power supply potential in a cascade manner to the plurality of semiconductor chips from a semiconductor chip that is different from the bottom-layered semiconductor chip and the top-layered semiconductor chip.