Patent Application
20060254810
The present disclosure relates generally to multilayer signal routing devices and, more particularly, to a technique for accommodating electronic components on a multilayer signal routing device.
The making of electrical connections between electronic components has long been accomplished using printed circuit boards (PCBs). The first such circuit boards had only a single routing layer on a top surface thereof for routing electrical signals between electronic components mounted thereon. These single routing layer circuit boards have severe limitations with regard to the number of electrical signals that can be routed between electronic components mounted on the same circuit board. That is, the number of electrical signals that can be routed between electronic components mounted on a single routing layer circuit board is limited by the amount of area on the single routing layer.
The area limitations associated with single routing layer circuit boards led to the development of multilayer PCBs. Such multilayer PCBs may be either single or double-sided and may have multiple routing layers on the surface of and buried within the multilayer PCBs. Thus, such multilayer PCBs have allowed a large increase in the number of electrical signals that may be routed between electronic components mounted on the same circuit board.
The use of multilayer PCBs has been particularly beneficial when using electronic components having high-density packages. That is, electronic components having high-density packages generally require multiple layers of a multilayer PCB to make electrical connections with other electronic components mounted on the same circuit board. In fact, the density of electronic component packages typically dictates the number of layers that must be provided by the multilayer PCB upon which the electronic components are mounted. While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, reliability and other problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components. For example, when making electrical connections between different layers in multilayer PCBs, a combination of electrically conductive traces and electrically conductive vias are generally used. While electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough. That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance, which can adversely affect signals propagating along each electrically conductive via. In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase.
To alleviate at least some of the above-mentioned adverse effects, it is often helpful to have resistive, capacitive, and/or inductive components electrically connected in series and/or parallel with an electrically conductive via, which is also electrically connected to a signal driver contact of an electronic component. However, this if often difficult to achieve since the signal driver contact may be located within the interior of a contact array of the electronic component, and thus there is no place to mount the resistive, capacitive, and/or inductive components. Even if the signal driver contact is located along the periphery of a contact array of the electronic component, there may still be no place to mount the resistive, capacitive, and/or inductive components since electronic components are now being placed ever closer together on the surfaces of PCB's and other types of multilayer signal routing devices.
One proposed solution to the problem of mounting resistive, capacitive, and/or inductive components since electronic components near a signal driver contact of an electronic component is to bury or embed the resistive, capacitive, and/or inductive components within a PCB or other type of multilayer signal routing device. However, the cost and maturity of suitable technologies for this proposed solution make it impractical.
In view of the foregoing, it would be desirable to provide a technique for mounting resistive, capacitive, and/or inductive components on a multilayer signal routing device near a signal driver contact of an electronic component that overcomes the above-described inadequacies and shortcomings.
According to the present disclosure, a technique for accommodating electronic components on a multilayer signal routing device is provided. In one particular exemplary embodiment, the technique may be realized as a method for accommodating electronic components on a multilayer signal routing device. Such a method may comprise determining a component space that is required to accommodate a plurality of electronic components on a surface of a multilayer signal routing device, and then forming at least one signal routing channel on at least the surface of the multilayer signal routing device, wherein the at least one signal routing channel has a channel space that is equal to or greater than the component space. The at least one signal routing channel formed on the surface of the multilayer signal routing device may have a vertical, horizontal, and/or diagonal orientation portion along the surface of the multilayer signal routing device.
In accordance with other aspects of this particular exemplary embodiment of the present disclosure, determining a component space may beneficially comprise determining a number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device, and then determining a required space for each of the number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device.
In accordance with further aspects of this particular exemplary embodiment of the present disclosure, forming at least one signal routing channel may beneficially comprise forming at least two relatively aligned electrically conductive micro-vias in the multilayer signal routing device coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
In accordance with additional aspects of this particular exemplary embodiment of the present disclosure, wherein the surface of the multilayer signal routing device is a secondary surface of the multilayer signal routing device, a plurality of electrically conductive pads may beneficially be formed on a primary surface of the multilayer signal routing device opposite the secondary surface of the multilayer signal routing device. If such is the case, at least two relatively aligned electrically conductive micro-vias may beneficially be formed in the multilayer signal routing device in electrical connection with at least two respective ones of the electrically conductive pads and coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. At least a portion of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. Also, an electrically conductive pad may beneficially be formed on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. If such is the case, at least one of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device in electrical connection with the electrically conductive pad formed on the secondary surface of the multilayer signal routing device and coinciding with the position of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. Of course, an electrically conductive trace may also beneficially be formed on the secondary surface of the multilayer signal routing device electrically connected to the electrically conductive pad formed on the secondary surface of the multilayer signal routing device.
In another particular exemplary embodiment, the technique may be realized as a novel multilayer signal routing device. Such a multilayer signal routing device may comprise a primary surface having a plurality of electrically conductive pads formed thereon, wherein a group of the plurality of electrically conductive pads is in respective electrical connection with a group of electrically conductive micro-vias formed in the multilayer signal routing device. Such a multilayer signal routing device may also comprise a secondary surface having a signal routing channel formed thereon coinciding with the location of the group of electrically conductive micro-vias, wherein the signal routing channel has a channel area on the secondary surface for accommodating an electronic component mounted on the secondary surface. The signal routing channel may have a vertical, horizontal, and/or diagonal orientation portion along the secondary surface of the multilayer signal routing device.
In accordance with other aspects of this particular exemplary embodiment of the present disclosure, the secondary surface may beneficially have an electrically conductive pad formed thereon within the signal routing channel. If such is the case, the electronic component may beneficially be mounted on the secondary surface within the signal routing channel in electrical connection with the electrically conductive pad formed on the secondary surface. Of course, the secondary surface may beneficially have an electrically conductive trace formed thereon, wherein the electrically conductive trace is in electrical connection with the electrically conductive pad formed on the secondary surface.
The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.
In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.
At the outset, it is helpful to refer to the techniques for reducing the number of layers in a multilayer signal routing device as have been substantially described in the above-referenced U.S. Provisional Patent Application No. 60/212,387, the above-referenced U.S. patent application Ser. No. 09/651,188 (now U.S. Pat. No. 6,388,890), the above-referenced U.S. patent application Ser. No. 10/101,211, the above-referenced U.S. patent application Ser. No. 10/126,700 (now U.S. Pat. No. 6,545,876), the above-referenced U.S. patent application Ser. No. 10/326,123, the above-referenced U.S. patent application Ser. No. 10/326,079, and the above-referenced U.S. patent application Ser. No. 10/407,460, all of which have been incorporated by reference herein in their entirety.
The above-referenced techniques are certainly beneficial for reducing the number of layers in a multilayer signal routing device. However, these techniques may be even more beneficial if used in conjunction with one or more of the several techniques described herein.
Referring to
In the embodiment of
At this point it should be noted that some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 may not be electrically connected to any electrically conductive pads formed on the primary side of the multilayer signal routing device portion 100. For example, some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 may be used for testing the electronic component when the electronic component is not mounted on the multilayer signal routing device portion 100.
While the signal routing channels 104 are very beneficial for reducing the number of layers in a multilayer signal routing device as described in the above-referenced techniques, the signal routing channels 104 may also be used to provide valuable space for mounting additional electronic components on the secondary side of the multilayer signal routing device portion 100 in accordance with an embodiment of the present disclosure. For example, referring to
At this point it should be noted that, as shown in
It should also be noted that the electrical connections 108 may be electrically conductive traces formed on the secondary side of the multilayer signal routing device portion 100. In such a case, the multiple additional electronic components 106 may have electrically conductive contacts (e.g., surface mount pads) which may be mounted on respective mating electrically conductive pads (not shown) formed on the secondary side of the multilayer signal routing device portion 100. Of course, these mating electrically conductive pads formed on the secondary side of the multilayer signal routing device portion 100 are electrically connected to respective electrically conductive traces.
Alternatively, the electrical connections 108 may be electrically conductive leads associated with the multiple additional electronic components 106. In such a case, the multiple additional electronic components 106 may be mounted on the secondary side of the multilayer signal routing device portion 100 with a non-electrically conductive adhesive while the electrically conductive leads are separately electrically connected to respective ones of the electrically conductive pads 102. Indeed, the multiple additional electronic components 106 may even be mounted on top of surface mount components, which themselves are mounted on the secondary side of the multilayer signal routing device portion 100 within the signal routing channels 104, thereby forming stacked component structures so as to further increase component density on the multilayer signal routing device portion 100.
As shown in
At this point it should be noted that an empirical prediction may be made regarding the total amount of space that is required to accommodate all of the additional electronic components 106 that are required for a particular design. For example, assuming a worst case signal-to-ground ratio of 2:1, and that each signal must be attached to one of the additional electronic components 106, the total number of additional electronic components 106 required for an electronic component having M×N array of electrically conductive contacts formed thereon is approximately (M×N)/3. Thus, the total amount of space that is required to accommodate all of the additional electronic components 106 that are required for a particular design is (M×N)/3*(space required for the additional electronic component 106, including any required clearance surrounding the additional electronic component 106). Once the total amount of space is determined, the required number and size of signal routing channels 104 may be created using the above-referenced techniques for reducing the number of layers in a multilayer signal routing device.
At this point it should be noted that the signal routing channels 104 may be configured in a variety of ways to achieve the total amount of space that is required to accommodate all of the additional electronic components 106. For example, referring to
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The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.
This patent application is a divisional of U.S. patent application Ser. No. 10/716,599, filed Nov. 20, 2003, which claims priority to U.S. Provisional Patent Application No. 60/427,865, filed Nov. 20, 2002, each of which is hereby incorporated by reference herein in its entirety. The above-referenced U.S. patent application Ser. No. 10/716,599 is a continuation-in-part of U.S. patent application Ser. No. 10/101,211, filed Mar. 20, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/651,188, filed Aug. 30, 2000, now U.S. Pat. No. 6,388,890, which claims priority to U.S. Provisional Patent Application No. 60/212,387, filed Jun. 19, 2000, each of which is hereby incorporated by reference herein in its entirety. The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/326,123, filed Dec. 23, 2002, now U.S. Pat. No. 7,069,650, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, and a continuation-in-part of U.S. patent application Ser. No. 10/126,700, filed Apr. 22, 2002, now U.S. Pat. No. 6,545,876, which is a continuation of the above-referenced U.S. patent application Ser. No. 09/651,188, each of which is hereby incorporated by reference herein in its entirety. The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/326,079, filed Dec. 23, 2002, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/126,700, and a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, each of which is hereby incorporated by reference herein in its entirety. The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/407,460, filed Apr. 7, 2003, now U.S. Pat. No. 7,069,646, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/126,700, a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/326,123, and a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/326,079, each of which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60427865 | Nov 2002 | US | |
| 60212387 | Jun 2000 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10716599 | Nov 2003 | US |
| Child | 11488799 | Jul 2006 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09651188 | Aug 2000 | US |
| Child | 10126700 | Apr 2002 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10101211 | Mar 2002 | US |
| Child | 11488799 | Jul 2006 | US |
| Parent | 09651188 | Aug 2000 | US |
| Child | 10101211 | Mar 2002 | US |
| Parent | 10326123 | Dec 2002 | US |
| Child | 10716599 | US | |
| Parent | 10101211 | Mar 2002 | US |
| Child | 10326123 | Dec 2002 | US |
| Parent | 10126700 | Apr 2002 | US |
| Child | 10326123 | Dec 2002 | US |
| Parent | 10326079 | Dec 2002 | US |
| Child | 10716599 | US | |
| Parent | 10126700 | Apr 2002 | US |
| Child | 10326079 | Dec 2002 | US |
| Parent | 10101211 | Mar 2002 | US |
| Child | 10326079 | Dec 2002 | US |
| Parent | 10407460 | Apr 2003 | US |
| Child | 10716599 | US | |
| Parent | 10126700 | Apr 2002 | US |
| Child | 10407460 | Apr 2003 | US |
| Parent | 10101211 | Mar 2002 | US |
| Child | 10407460 | Apr 2003 | US |
| Parent | 10326123 | Dec 2002 | US |
| Child | 10407460 | Apr 2003 | US |
| Parent | 10326079 | Dec 2002 | US |
| Child | 10407460 | Apr 2003 | US |
