The present invention is generally directed to an electronic assembly and, more specifically, to a technique for defining a wettable solder joint area for an electronic assembly substrate.
Traditionally, solder stops (i.e., solder masks) have been printed onto a substrate to define wettable solder joint areas. Unfortunately, the utilization of a solder stop may be insufficient to avoid wicking of the solder along side-walls of conductors formed on outer surfaces of the substrate. For example, various electronic assemblies that have utilized thermally conductive ceramic substrates, with thick copper conductors or thick film conductors, have experienced solder wicking along side-walls of the conductors. Further, while a single-sided solder stop may be replaced with a multi-sided solder stop, e.g., a four-sided solder stop made of a printed thick film, utilization of a multi-sided solder stop may significantly impact the minimum conductor width to the point that the conductors cannot be connected to fine pitch integrated circuit (IC) chips. Further, the printing and firing of traditional solder stops has required additional material and processing steps.
In addition to utilizing solder masks to identify a wettable solder joint area for an electronic assembly, solder masks have been utilized to prevent additional solder from attaching to conductive metal patterns during wave solder processes, as well as to provide a low-level moisture barrier between conductors. In general, solder masks are photo-imageable or a pattern printed polymer that is applied to outer layer metal conductive patterns of a printed circuit board (PCB) or other substrate to aid in the assembly or improve the performance of the substrate. While polymer solder masks have been a PCB industry standard for many years, a number of problems have been attributed to the utilization of solder masks in electronic assemblies. For example, a typical solder mask is applied as a thin layer of epoxy over conductive patterns (i.e., circuits or traces) formed on the substrate. Unfortunately, when the solder mask is exposed to severe environments, such as temperature cycling or temperature extremes, the solder mask may mechanically fail, resulting in cracks in the solder mask. These cracks in the solder mask can propagate and cause failures of conductive circuits on the substrate, as well as failures of the solder joints that connect various electrical devices to the conductive circuits.
In electronic assemblies that utilize flip chips, a solderable surface is typically defined on two sides by the edge of a copper conductor and on the other two sides by a polymer solder mask. As such, the thickness of the solder mask between the conductors is often equal to or greater than the conductor height, e.g., 0.0018 inch, while the thickness of the solder mask on the surface of the conductor is significantly lower, e.g., 0.0005 inch. It should be appreciated that the presence of the solder mask near the flip chip solder connection site limits the ability of fluids to flow around an associated solder bump, resulting in the inability to remove flux residues after reflow. Further, the solder mask may inhibit the application of an underfill material for electronic assemblies that require encapsulation for environmental considerations.
On the other hand, solder masks typically prevent electrical performance problems (when a substrate transitions through a dew point) by preventing water droplets from shorting adjacent conductors. However, as noted above, solder masks are usually made of an epoxy, which is a hydroscopic material, that tends to absorb moisture over time. This absorbed moisture may cause electrical performance problems for the electronic assembly. Further, the mechanical properties of solder masks are typically not optimized for coefficient of thermal expansion (CTE) control and adhesion to other polymers. Thus, when a substrate is encapsulated, the solder mask may be a weak link and limit system performance, due to structural failure at the interface between the solder mask and the substrate or between the solder mask and the encapsulation material. The relatively high CTE of a typical solder mask may also lead to excessive stress of flip chip solder joints, due to thermal expansion of the mask located under the chip. Additionally, the relatively low electrical conductivity of the solder mask, relative to metals such as copper, and other electrical properties of the solder mask may have an adverse affect on electrical performance at higher frequencies, e.g., above 1 GHz, as the presence of the solder mask contributes to distributed high frequency elements, which can increase transmission loss and severely degrade performance.
What is needed is a technique for defining a wettable solder joint area for an electronic assembly substrate that provides an effective solder stop for thick conductors and does not negatively impact the pitch of the conductor. Further, it would be advantageous if the technique reduced the materials and the number of processing steps required to define a wettable solder joint area, while reducing electrical performance degradation of an associated electronic assembly, attributable to the use of traditional solder masks.
The present invention is directed to a technique for defining a wettable solder joint area for an electronic assembly. According to the technique, a substrate that includes at least one conductive trace has a nickel layer provided on the conductive trace. Gold is then selectively applied on the nickel layer in a desired pattern. An exposed portion of the nickel layer that does not include the gold in the desired pattern is then oxidized. Finally, a solder is applied to the gold layer, with the oxidized nickel layer providing a solder stop and defining a wettable solder joint area.
According to another aspect of the present invention, the selective application of gold on the nickel layer includes depositing the gold in a gold layer on the nickel layer, masking a portion of the gold layer, removing a portion of the gold from the unmasked portions of the gold layer and removing the mask from the gold layer.
According to a different embodiment of the present invention, the selective application of gold on the nickel layer includes masking a portion of the nickel layer, depositing the gold on the unmasked portions of the nickel layer to form the gold layer and removing the mask from the nickel layer.
According to one embodiment of the present invention, the nickel is an electroless nickel. According to another embodiment of the present invention, the substrate is a ceramic substrate. According to this aspect of the present invention, the ceramic substrate is one of a silicon nitride substrate and an aluminum nitride substrate. According to a different aspect of the present invention, the conductive trace is a copper trace. According to yet another embodiment of the present invention, the conductive trace is a printed thick film conductor. According to this aspect, the printed thick film conductor is a silver palladium conductor.
These and other features, advantages and objects of the present invention will be further understood and appreciated by those skilled in the art by reference to the following specification, claims and appended drawings.
The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
According to the present invention, a technique is disclosed herein that provides an alternative to typical printed solder stops. According to one aspect of the present invention, an electroless nickel-gold finish, which is a standard finish for copper on ceramic and has become increasingly popular for thick film conductors, is utilized. In a typical electronic assembly that utilizes thick films, a layer of palladium (Pd) is typically deposited between the nickel (Ni) and gold (Au) layers. Typical assemblies include a common base conductor layer, e.g., a copper layer, a nickel layer and a common final layer, typically of gold (Au), which is highly solderable. It should be appreciated that nickel oxidizes relatively easily and does not wet to solder in the oxidized state. According to the present invention, the oxidized nickel (or passivated nickel) is utilized to define a wettable solder joint area for an electronic assembly. Thus, according to the present invention, a zero footprint solder stop is implemented that is effective on thick side-walls of copper traces, as well as on side-walls of printed thick film conductors, such as silver palladium conductors.
According to one embodiment of the present invention, the wettable solder joint areas, which include pads of gold, are surrounded by an oxidized nickel finish, which does not provide a wettable solder joint area. Thus, the oxidized nickel formed on the conductor and the conductor side-walls acts as solder stop, which eliminates undesirable solder loss along the conductor side-walls, and maintains a desired solder joint thickness, thus, improving the reliability of the solder joint.
With reference to
It should be appreciated that a wettable solder joint area may be achieved through a number of processes that are encompassed by the present invention. According to the present invention, a substrate that includes at least one conductive trace has a nickel layer deposited on the conductive trace. Gold is then selectively applied on the nickel layer in a desired pattern. An exposed portion of the nickel layer that does not include the gold in the desired pattern is then oxidized. Finally, a solder is applied (e.g., through a solder reflow process) to the gold layer, with the oxidized nickel layer providing a solder stop and defining a wettable solder joint area.
According to one embodiment of the present invention, as is depicted in
Accordingly, a technique has been described herein that eliminates undesirable solder loss, along the conductor side-walls, provides a zero footprint and allows for a reduction in conductor pitch, if needed to match the pitch of a particular flip chip.
According to another embodiment of the present invention, a passivated nickel (nickel oxide) is utilized on non-solderable sites of a conductive copper pattern of a substrate, e.g., a printed circuit board (PCB), to provide essentially the same features as a polymer solder mask, while addressing the performance degradation of the electronic assembly attributable to the polymer solder mask. In general, a nickel coating over the copper is passivated, via an oxidation chemical reaction, to provide a relatively thin non-solderable electrically non-conductive surface treatment. The surface treatment solves a number of technical issues that are present with electronic assemblies that implement polymer solder masks.
For example, the passivation of the nickel surface results in a hard non-solderable surface that does not crack, peel or otherwise mechanically fail, when exposed to temperature cycling or temperature excursions typically seen in an automotive environment. Further, utilizing an oxidized nickel to provide a solder mask beneath a flip chip facilitates easier cleaning under the flip chip and easier application of an underfill material. The oxide formed on the nickel is also electrically non-conductive and, therefore, provides moisture protection during transition through a dew point and is inorganic and, thus, does not absorb moisture. Further, the mechanical properties of the nickel oxide insignificantly contribute to thermally induced stresses. Additionally, the nickel oxide does not adversely affect electrical performance at high frequencies. Thus, according to the present invention, a passivated nickel is used under a chip as a solder stop to replace traditional polymer solder masks, which have adversely affected the performance of an associated electronic assembly.
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Accordingly, an electronic assembly has been defined herein, which utilizes passivated solder to contain a solder in a desired location during a solder reflow process. Such an assembly is particularly advantageous when implemented in an automotive environment, as it does not include a solder mask between a die and a substrate, which can negatively impact the performance of the electronic assembly.
The above description is considered that of the preferred embodiments only. Modifications of the invention will occur to those skilled in the art and to those who make or use the invention. Therefore, it is understood that the embodiments shown in the drawings and described above are merely for illustrative purposes and not intended to limit the scope of the invention, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents.