Patent Application
20060211171
The present invention relates generally to flip-chip fabrication methods and substrates suitable for flip-chip assembly.
The most popular approach to flip-chip integrated circuit (IC) assembly is to use lead-free or eutectic Pb/Sn solder, placing the IC on the substrate, reflowing the solder joints at high temperature, and finally dispensing and curing “capillary flow” underfill material to improve the interconnect reliability. Another approach involves “no-flow” underfill dispensing on the substrate, placing a bare IC on the substrate, using moderate pressure to push the underfill out of substrate bond pads, followed by simultaneous solder reflow and underfill cure. A leading edge flip-chip process in manufacturing is around 150-180 μm area array and 50 μm pitch peripheral with 100-125 μm pitch area array and 20-50 μm pitch peripheral flip-chip in R&D around the world. Both of the approaches described above have severe technical limitations for future systems with <50 μm pitch flip-chip interconnection. The driver for such a reduction in pitch is two-fold; higher I/O density on the IC due to the higher transistor density, and lower stand-off height interconnects to reduce electrical parasitics and enable higher signal speed and bandwidth.
The critical property requirements for underfill materials for such fine-pitch interconnects are low coefficient of thermal expansion (CTE) close to that of the solder used for reflow, and high elastic modulus (8-10 GPa) to absorb strains induced by CTE mismatch between chip and substrate. The current approach of capillary flow underfill is limited by flow properties of the polymer based underfill materials which use a high volume of ceramic fillers to reduce the coefficient of thermal expansion. The no-flow approach also has limitations of being able to clear the bond pads of underfill material that is highly filled for low CTE and high modulus.
It would be desirable to have a flip-chip fabrication method that improves upon the conventional approaches described above. It would also be desirable to provide the ability to select any underfill material with appropriate CTE, modulus and other properties without being restricted by the viscosity and flow characteristics of the underfill and its ability to fill very small chip-to-substrate gap heights.
The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
Disclosed herein is a novel approach to interconnect assembly and underfill processing applicable to standard lead-free, eutectic solder, and other alloy reflow based flip-chip interconnects, copper, nickel or other metal/alloy pillar or column interconnects, gold stud bump connections (bonded using gold-to-gold thermosonic bonding), conductive polymer bumps (bonded using a reflow process), composite post flexible interconnects, and all other interconnect types for low stand-off chip to package interconnects in the 10-100 μm peripheral and area array I/O pitch. The approach and processes disclosed herein utilize underfill materials with tailored properties along with a variety of patterning techniques to produce openings in underfill material disposed on a substrate that are used as an alignment guide for flip-chip attachment to the substrate. For example, openings in the underfill materials may be achieved using laser patterning, photolithographic patterning, stamping, imprinting, plasma etching, dry etching, or wet chemical etching, for example. The disclosed process methods are also relevant to package substrates with embedded ICs buried in the core or build-up layers wherein the interconnection from chip to substrate is formed using any of the techniques listed above.
Referring now to the drawing figures,
More particularly, in the processes 20, 20a illustrated in
One novel aspect of the disclosed processes 20, 20a is the ability to use underfill materials 13 with tailored properties, because the viscosity of the underfill material 13 is not critical for dispensing (compared to current capillary flow processes) and flow of underfill material 13 during chip placement 28 is not critical (compared to current no-flow processes). The photolithographic or laser patterning processes 20, 20a also allows for extremely fine pitch without the problems of dispensing underfill material 13 into the tight space between I/O bumps common to conventional practices. The templated underfill material 13 on the substrate 11 also acts an alignment guide for chip placement 28 enabling low cost equipment to be used for 10-20 μm pitch flip-chip assembly.
One of the potential issues encountered during early work on these processes 20, 20a was the effect of photolithographic or laser patterning on the “degree of cure” of the underfill material 13 that could affect the flow of the underfill material 13 during final solder reflow. A novel approach was developed to solve this potential problem. The underfill material 13 deposited on the substrate 11 may be fully cured prior to patterning as is common in “microvia” substrates today. However, an additional thin layer of underfill material 13a (illustrated in dashed lines in
Thus, flip-chip fabrication methods employing laser and photolithographic underfill patterning processes have been disclosed. It is to be understood that the above-described embodiments are merely illustrative of some of the many specific embodiments that represent applications of the principles discussed above. Clearly, numerous and other arrangements can be readily devised by those skilled in the art without departing from the scope of the invention.
| Number | Date | Country | |
|---|---|---|---|
| 60663135 | Mar 2005 | US |
