Patent Application
20170250141
The present invention relates to wiring circuit boards (interposers) and semiconductor devices, particularly to a wiring circuit board provided between a package substrate and a semiconductor element, and to a semiconductor device provided with a wiring circuit board to be connected to a semiconductor element.
Package substrates are used to connect a fine pitch semiconductor element to an external substrate such as a daughter board. Such package substrates are formed of a material such as ceramics or resins.
Since a ceramic package substrate uses a sintered metallized material, the resistance can be high. Further, since ceramics have a high dielectric constant, it is difficult to mount a high-frequency and high-performance semiconductor element to the ceramic package substrate. On the other hand, since a resin package substrate uses copper wiring obtained by plating, the wiring resistance can be decreased. Since resins have a low dielectric constant, it is relatively easy to mount a high-frequency and high-performance semiconductor element to the resin package substrate.
There are techniques for interposing an interposer (wiring circuit board) between the package substrate and a semiconductor element, for example, as described in PTLs 1 to 4.
In recent years, interposers in which silicon or glass is used as a material for a substrate have been thoroughly studied and have attracted attention as high-end interposers.
Such interposers using silicon or glass as a base material are characterized by the use of techniques called TSV (through-silicon via) or TGV (through-glass via) for forming a through hole inside the substrate to fill the through hole with a conductive material. A through electrode formed by such a technique has a reduced wiring length because the front and back surfaces are connected by a minimum distance, thereby allowing for high electrical properties such as high speed signal transmission.
Such a through electrode has a coefficient of linear expansion equal or close to that of the semiconductor element, reduces dimensional changes of the substrate on heating, and enables higher density packaging and higher density wiring. In addition, employment of such a through electrode enables parallel multi-pin connection, and accordingly good electrical properties can be obtained without increasing the speed of LSI. This may allow for lower power consumption.
In particular, glass interposers using glass as a material for the substrate are attracting attention in recent years. Among other things, the use of such glass interposers is expected to lead to cost reduction. Although silicon interposers are manufactured only in a wafer size, glass interposers can be mass-processed using a large-sized panel. This may help to solve cost issues, which have been a major problem of high-end interposers.
PTL 1: JP 2001-102479 A
PTL 2: JP 2002-373962 A
PTL 3: JP 2002-261204 A
PTL 4: JP 2000-332168 A
Unfortunately, in designing glass interposers, there are some problems to be overcome. One of such problems is that since glass substrates have a low thermal conductivity and conductive materials of achieving adhesion to glass are limited, the heat of the semiconductor element is insufficiently dissipated, thereby inhibiting driving of the semiconductor element, or due to the difference in CTE (coefficient of thermal expansion) between the semiconductor element and the component material for the glass interposer, the electrical connection therebetween may be broken. In addition, the glass interposers may create a phenomenon that a conductive layer pattern made of copper or the like is detached from the surface of the glass in a high temperature process during mounting or in a temperature cycle of reliability tests.
The present invention has been made to solve the problem set forth above, and has an object to provide a wiring circuit board, a semiconductor device, a method of manufacturing a wiring circuit board, and a method of manufacturing a semiconductor device which can efficiently dissipate heat generated from a semiconductor element to improve adhesion between a glass substrate and a conductive layer pattern, thereby having higher reliability.
A wiring circuit board according to the present invention has a base material having a through hole, an insulative resin layer laminated on the base material and having a conductive via formed therein, and a wiring group laminated on the insulative resin layer, and the wiring circuit board includes an inorganic adhesive layer formed in the through hole, a hollow through electrode formed by laminating a first conductive layer on the inorganic adhesive layer, a filling resin formed by filling a mixture of a metallic powder and a resin material in the through electrode, and a second conductive layer covering upper and lower ends of the through electrode.
A semiconductor device according to the present invention includes the above wiring circuit board and a semiconductor element mounted on the wiring circuit board.
A method of manufacturing a wiring circuit board according to the present invention includes the steps of: forming a through hole in a base material; forming a first inorganic adhesive layer made of an inorganic material on both surfaces of the base material and an inner peripheral surface of the through hole; forming a hollow through electrode in the through hole by laminating a first conductive layer made of a conductive material on the first inorganic adhesive layer; filling a filling resin composed of a mixture of a metallic powder and a resin material in the through electrode; thinning the first conductive layer laminated on both surfaces of the base material; forming a second conductive layer made of a conductive material to cover both ends of the first conductive layer in the through hole to cover upper and lower ends of the through electrode and to form a first wiring group; forming an insulative resin layer covering the first wiring group; forming a via hole in a portion of the insulative resin layer on the first wiring group; and forming a second wiring group made of a conductive material, and a conductive via in the insulative resin layer.
Another method of manufacturing a wiring circuit board according to the present invention may include the steps of: forming a through hole in a base material; forming a first inorganic adhesive layer made of an inorganic material on both surfaces of the base material and an inner peripheral surface of the through hole; forming a hollow through electrode in the through hole by laminating a first conductive layer made of a conductive material on the first inorganic adhesive layer; filling a filling resin composed of a mixture of a metallic powder and a resin material in the through electrode; removing the first inorganic adhesive layer and the first conductive layer laminated on both surfaces of the base material; forming a second inorganic adhesive layer made of an inorganic material on both surfaces of the base material and the through electrode; forming a second conductive layer made of a conductive material on the second inorganic adhesive layer, covering upper and lower ends of the through electrode and forming a first wiring group; forming an insulative resin layer covering the first wiring group; forming a via hole in a portion of the insulative resin layer on the first wiring group; and forming a second wiring group made of a conductive material, and a conductive via in the insulative resin layer.
A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a wiring circuit board according to any one of the above methods of manufacturing a wiring circuit board; forming a conductive pad on the wiring circuit board; and fixing a semiconductor element on the conductive pad.
According to the present invention, efficient heat dissipation of a semiconductor element through a wiring circuit board enables suppression of a temperature rise of a semiconductor element and stabilization of driving. Further, according to the present invention, it is possible to provide a wiring circuit board, a semiconductor device, a method of manufacturing a wiring circuit board, and a method of manufacturing a semiconductor device by preventing detachment of a conductive layer pattern due to thermal expansion and thermal contraction, thereby ensuring higher reliability.
With reference to the drawings, embodiments of the present invention will be described.
With reference to
(Configuration of Wiring Circuit Board 100)
As shown in
The base material 1 is a substrate composed of glass (glass substrate) containing SiO2 as a main component, and includes the through hole 13.
The glass substrate has a thermal conductivity in the range of 0.55 to 0.75 W/m·k and the insulative resin has a thermal conductivity of 0.6 W/m·k or less, which are both relatively low. Cu used for the conductive layers 5 has a high thermal conductivity that is in the range of 80 to 400 W/m·k. The filling resin 14 of the present invention has a thermal conductivity that is in the range of 1 to 20 W/m·k, thereby achieving a thermal conductivity effect 2 to 40 times that of the insulative resin. The thermal conductivities were measured with a laser flash thermal constant analyzer in compliance with JIS:R1611, JIS:R1650-3, and JIS:H7801.
The base material 1 has a coefficient of thermal expansion, which is in the range of 3 to 4 ppm/° C. for low expansion glass and in the range of 8 to 9 ppm/° C. for soda lime glass, and can be controlled so as to be in the range of 3 to 9 ppm/° C. by the manufacturing method used or by adding metal components, such as Na. The coefficients of thermal expansion were measured in compliance with JIS:R3102 and JIS:K7197 by using a TMA (thermomechanical analysis).
In the method of forming the through hole 13 in the base material 1, one can use CO2 laser, UV laser, pico-second laser, femto-second laser, excimer laser, electric discharge machining, photosensitive glass, blast machining, or the like, which may be selected depending on the thickness of the base material 1 or the diameter of the through hole 13. When photosensitive glass is irradiated with ultraviolet rays, a metal colloid is formed inside, thereby improving solubility in hydrofluoric acid. This is a material capable of forming a through hole by using a difference in solubility in a glass degradation liquid between an irradiated portion and non-irradiated portion.
Materials of the inorganic adhesive layers 4a and 4b include materials achieving high adhesiveness between the base material 1 and the conductive material, such as tin oxide, indium oxide, zinc oxide, nickel (coefficient of thermal expansion: 15 ppm/° C.), nickel phosphorus, chromium (coefficient of thermal expansion: 8 ppm/° C.), chromium oxide, aluminum nitride, copper nitride, aluminum oxide, tantalum (coefficient of thermal expansion: 6 ppm/° C.), titanium (coefficient of thermal expansion: 9 ppm/° C.), and copper (coefficient of thermal expansion: 16 ppm/° C.).
The above materials of the inorganic adhesive layers 4a and 4b can be used alone or as a single layer formed of a composite material containing two or more of the above materials, such as an ITO film (coefficient of thermal expansion: 9 ppm/° C.). Further, the above materials of the inorganic adhesive layer 4 can be used as a laminated film of two or more layers formed of a composite material containing two or more of the above materials, such as a film of chromium/copper or titanium/copper.
The inorganic adhesive layers 4a and 4b are provided to improve adhesion of the base material 1 with the through electrode 3 (conductive layer 5a) and the conductive layer 5b. In addition, since the inorganic adhesive layers 4a and 4b have a coefficient of thermal expansion higher than that of the base material 1, it is possible to reduce stress across the layers caused by the difference in the coefficients of linear expansion of the through electrode 3 (conductive layer 5a) and the conductive layer 5b from the base material 1.
Film thicknesses of the inorganic adhesive layers 4a and 4b are not specifically limited, but may be in the range from 0.1 μm or more to 1 μm or less to obtain adhesion and to achieve the effect of reducing a difference in the coefficients of thermal expansion. Further, methods of forming the inorganic adhesive layers 4a and 4b are not specifically limited, but include sputter deposition, non-electrolytic plating, or the like.
The inorganic adhesive layer 4a corresponds to the first inorganic adhesive layer, and the inorganic adhesive layer 4b corresponds to the second inorganic adhesive layer.
The through electrode 3 is made of a conductive material. The through electrode 3 in a hollow shape is formed of the conductive layer 5a which is formed on the inorganic adhesive layer 4a provided in the through hole 13. Examples of the conductive material forming the through electrode 3 include metals, such as copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead, which may be used alone or as a stack or a compound of any of these metals. Materials having high adhesiveness to the inorganic adhesive layers 4 and high electrical connection stability may be selected.
Instead of the conductive layer 5a, the material for the through electrode 3 may be a filling resin which fills the inside of the inorganic adhesive layers 4, i.e. a mixture of a resin material and a powder of at least one of the above forming metals for the first conductive layer 5a, after the inorganic adhesive layer 4 has been formed.
A method of forming the conductive layer 5a may be conformal plating, including non-electrolytic plating and electroplating, for formation. Since the density of semiconductor devices is becoming higher, wiring is becoming finer, and the diameter of the through electrode 3 is becoming smaller. Accordingly, the through electrode 3 has a high aspect ratio, and therefore there is a region not available for filled plating. In the high aspect ratio region, the through electrode 3 may be formed by conformal plating. In the low aspect ratio region, the through electrode 3 may be formed by filled plating.
In the form obtained through conformal plating, a through hole-shaped hole is left at the center of the through hole 13, which may be filled with the filling resin 14 by screen printing.
In the form obtained through filled plating, thicker conductive layer 5a (first conductive layer) is laminated on both surfaces of the base material 1. Hence, the conductive layer 5a laminated on both surfaces of the base material 1 may be thinned to form fine wiring on the base material 1. At this point, it may be so configured that the surface of the base material 1 is polished to expose the upper and lower ends of the through electrode 3, followed by laminating the inorganic adhesive layer 4b (second inorganic adhesive layer) and the conductive layer 5b (second conductive layer) on the base material 1 to form a wiring group (refer to
The conductive layer 5b is made of a conductive material and is formed on both surfaces of the base material 1 via the inorganic adhesive layer 4b. Examples of the conductive material forming the conductive layer 5b include metals, such as copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead, which may be used alone or as a laminate or a compound of any of the metals. Materials having high adhesiveness to the inorganic adhesive layers 4b and high electrical connection stability may be selected.
In addition, examples of the conductive material forming the conductive layer 5b may be a conductive paste that is a mixture of a resin material and a powder of at least one metal of the above materials. Further, methods of forming the conductive layer 5 are not specifically limited, but include non-electrolytic plating and electroplating.
The land 6 is formed on the upper and lower ends of the through electrode 3 or on the wiring routed from the through electrode 3 via the conductive layer 5b. The land 6 may be at the same level, for example, as the surface of the base material 1, or may be at a level higher, by several microns, than the surface of the base material 1.
As shown in
The insulative resin layer 7 is formed on the conductive layer 5b. A necessary number of the insulative resin layers 7 are stacked. The number of the insulative resin layers 7 may be decided depending on, for example, the design of the product.
Materials of the insulative resin layer 7 include an epoxy/phenol resin, a polyimide resin, a cycloolefin, and a PBO resin, which can be used alone or as a composite material containing at least two or more of these materials. In this case, for example, the material of the insulative layer 7 may have a coefficient of thermal expansion in the range of 30 to 100 ppm/° C., which is higher than that of the conductive material, and may have a high elastic modulus to cover the conductivity layer 5b for reduction of the stress applied between the layers of the conductive layer 5b and the substrate 1, thereby exerting an effect of preventing detachment of the conductive layer 5b.
Examples of the material for the insulative resin layer 7 include, but are not specifically limited to, a dry film and a liquid photo solder resist.
In the wiring group 8, a necessary number of layers are stacked. The number of layers of the wiring group 8 may be decided depending on, for example, the design of the product. Methods of forming the wiring group 8 are not specifically limited, but the wiring group 8 may be formed by using non-electrolytic plating layer or a sputtered film as a seed layer, and thickening by electrolytic plating, followed by patterning using a semi-additive process or a subtractive process.
The conductive via 9 is formed in the insulative resin layer 7 so as to electrically connect the conductive layer 5 to the wiring group 8. The conductive via 9 is formed by a process of filling the via hole formed in the insulative resin layer 7 with a conductive material, such as conformal plating.
Methods of forming the via hole in the insulative resin layer 7 may be selected depending on, for example, the material of the insulative resin layer 7. When the material of the insulative resin layer 7 is a heat-curable resin, the via hole may be formed by a process using a CO2 laser, UV laser, or the like, which is followed by a desmearing process to remove smears generated in the laser process. When the material of the insulative resin layer 7 is a photosensitive resist, the via hole may be formed by photolithography.
As described above, the wiring circuit board 100 of the present embodiment is a multi-layer interposer having through electrodes. According to the wiring circuit board 100 of the present embodiment, higher conductive reliability is achieved between the wiring groups 8 formed on both surfaces of the base material 1. The necessary numbers of layers of the insulative resin layer 7 and the wiring group 8, and the shape and the height of the metal layer of the conductive pad shown in
(Configuration of Semiconductor Device 200)
As shown in
The semiconductor element 11 is mounted on one surface (upper surface in
As described above, according to the semiconductor device 200 of the present embodiment, the heat generated by the semiconductor element 11 is more highly effectively dissipated toward the printed board side via the through electrode 3 of the wiring circuit board 100 by optimizing the material of the filling resin 14 in the through electrode 3 between the wiring circuit board 100 and the semiconductor element 11 to be connected thereto. Furthermore, more highly reliable connection can be obtained by preventing the wiring group 8 from being detached from the substrate 1 during mounting.
With reference to
As shown in
Examples of the present invention will be described in conjunction with a method of manufacturing a wiring circuit board and a method of manufacturing a semiconductor device.
With reference to
A method of manufacturing a wiring circuit board 100 according to Example 1 includes steps of forming a through hole, forming an inorganic adhesive layer, forming a conductive layer and a through electrode, forming a land, forming an insulative resin layer, forming a via hole, and forming a wiring group and a conductive via.
As shown in
As shown in
As shown in
As shown in
As shown in
In the step of forming a wiring group and a conductive via, the conductive via 9 was formed by filling the inside of the via hole formed in the insulative resin 7 with copper by conformal plating. For the wiring group 8, a non-electrolytic copper plating layer was formed as a seed layer on the insulative resin 7. Further, on the seed layer, a resist pattern in which a portion corresponding to a wiring group 8 (refer to
Then, as shown in
A method of manufacturing a semiconductor device 200 of Example 1 included steps of forming a conductive pad 15 on the wiring circuit board 100 produced by the above method of manufacturing a wiring circuit board, and fixing the semiconductor element 11 on the conductive pad.
In the step of forming a conductive pad, a photosensitive solder resist 12 was laminated on the substrate 1 for light exposure and development, and the conductive pad 15 was formed by Ni/Au plating.
In the step of fixing a semiconductor element, the semiconductor element 11 was fixed onto the conductive pad 15 by soldering.
In Example 1, the wiring group 8 on one surface was formed of two layers, the solder resist 12 was provided as a surface coating layer, and the surface of the conductive pad 15 was treated with Ni/Au. However, the configurations are not specifically limited thereto.
Example 2 of the present invention will be described in conjunction with
A method of manufacturing a wiring circuit board 100 of Example 2 includes steps of forming a through hole, forming an inorganic adhesive layer, forming a conductive layer and through electrode, forming a land, forming an insulative resin layer, forming a via hole, and forming a wiring group and conductive via.
As shown in
Next, as shown in
Next, as shown in
Next, in the step of forming a land, the laminate on the substrate 1 were polished by chemical polishing until the thickness thereof became 3 μm to remove the conductive paste protruding from the through hole 13. Then, electrolytic copper plating was applied over the conductive paste for the through-hole portion to form a 5 μm thick conductive layer 5c serving as a lid, on the surface of the base material 1, as shown in
Next, as shown in
Then, in the step of forming a wiring group/conductive via, the conductive via 9 was formed by filling the inside of the via hole formed in the insulative resin 7 by conformal copper plating. For the wiring group 8, a non-electrolytic copper plating layer was formed as a seed layer on the insulative resin 7. Further, on the seed layer, a resist pattern in which a portion corresponding to wiring group 8 (refer to
A method of manufacturing a semiconductor device 200 in Example 2 of the present invention included steps of forming a conductive pad 15 on the wiring circuit board 100 produced by the above method of manufacturing a wiring circuit board, and fixing the semiconductor element 11 on the conductive pad.
In the step of forming a conductive pad, a photosensitive solder resist 12 was laminated on the substrate 1 for light exposure and development, followed by Ni/Au plating to form the conductive pad 15.
In the step of fixing a semiconductor element, the semiconductor element 11 was fixed onto the conductive pad 15 by soldering.
In Example 2, the wiring group 8 on one surface was formed of two layers, the solder resist 12 was provided as a surface coating layer, and the surface of the conductive pad was treated with Ni/Au. However, the configurations are not particularly limited thereto.
Comparative example 1 will be described in conjunction with
As shown in
Next, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Next, as shown in
Then, conductive vias were formed by conformal plating. The inner diameters of the conductive vias were set to 6 μm. For the wiring group 8, a non-electrolytic copper plating layer was formed as a seed layer on the insulative resin 7. Further, on the seed layer, a resist pattern in which a portion corresponding to the wiring group 8 (refer to
As a method of manufacturing the semiconductor device 200 of Comparative example 1, a photosensitive solder resist 12 was laminated on the substrate 1 for light exposure and development, and the conductive pad 15 was formed by Ni/Au plating on the wiring circuit board 100 manufactured by the above method of manufacturing a wiring circuit board. Then, the semiconductor element 11 was fixed to the conductive pad 15 by soldering.
A semiconductor device according to Comparative example 2 was manufactured in a manner similar to the semiconductor device according to Comparative example 1, except that the purpose of the through hole 13 formed in the substrate 1 was only to achieve electrical conductivity, and the thermal via was not formed. The diameter of the through hole 13 formed in the substrate 1 was set to 50 μm at the top.
A semiconductor device according to Comparative example 3 was manufactured in a similar manner to the semiconductor device according to Example 1 except that the inorganic adhesive layer 4a was not formed.
(Evaluation of Thermal Conductivity)
The thermal conductivity was evaluated using the semiconductor devices fabricated in Examples 1 and 2, and Comparative Examples 1 and 2. The thermal conductivity was evaluated by thermal resistance (Rja [° C/W]: Thermal Resistance between Junction of Semiconductor Components-Ambient Temperature). A higher thermal resistance indicates less propagation of temperature. The ambient temperature was measured using a T thermocouple (wire diameter of Φ0.8 mm, copper-constantan), and the junction temperature was measured using a thermal chip. The diode in the thermal chip was used for obtaining the junction temperature and the resistor therein was used as a heat source. The junction temperature was obtained using the voltage drop due to the temperature at both ends of the diode.
Table 1 shows the thermal resistances measured using the semiconductor devices according to Examples 1 and 2, and Comparative examples 1 and 2.
As shown in Table 1, the thermal resistance of the semiconductor device according to Examples 1 and 2 was lower than both of the semiconductor devices of Comparative examples 1 and 2. Accordingly, it was confirmed that by filling the first conductive layer 5 in the through electrode 3 with the filling resin 14 having thermal conductivity and covering the upper and lower ends of the through electrode 3 with the second conductive layer, the wiring circuit board 100 was able to dissipate heat of the semiconductor element 11 by thermal conduction via the wiring group and the through electrode 3 of the substrate 1. It was also confirmed that by filling the through electrode 3 with the filling resin 14 having a high thermal conductivity, heat resistance was improved by approximately 30% in comparison with Comparative example 1.
The semiconductor device according to Comparative example 1 had a thermal via for achieving thermal conductivity. The filling resin 94 filled in the thermal via, however, had a low thermal conductivity and the filling resin 94 with a low thermal conductivity occupied approximately 70% of the volume of the thermal via. Thus, it was confirmed that heat dissipation was low in comparison with those of Examples 1 and 2. Further, it was confirmed that the heat dissipation properties of the semiconductor device according to Comparative example 2 were low, since the thermal via was not formed therein.
In Examples 1 and 2, and Comparative examples 1 and 2, the inorganic adhesive layers 4 were formed and the conductive layers 5 were formed, thereby achieving higher adhesion to the substrate 1 made of low expansion glass. However, in Comparative example 3 with no inorganic adhesive layer 4a, there were no adhesion of the conductive layers to the substrate 1, thereby failing to obtain a wiring circuit board.
From Example 1, it was confirmed that removal of the first conductive layer on the surface of the substrate 1 and formation of the second inorganic adhesive layer and the second conductive layer 5 could lead to obtaining a wiring circuit board 100 that enabled easy control of the thickness of the conductive layers immediately above the substrate 1 and had high adhesion between the substrate 1, or the surface of the filling resin 14, and the conductive layers 5.
From Example 2, it was confirmed that thinning of the first conductive layer on the surface of the substrate 1 and formation of the second conductive layer 5 could lead to obtaining a wiring circuit board 100 that enabled omission of the step of forming the second inorganic adhesive layer and had high adhesion between the thinned first conductive layer and the second conductive layer, and high adhesion between the surface of the filling resin 14 and the second conductive layer.
As described above, according to the present invention, it is possible to dissipate the heat generated by the semiconductor element 11 to the printed board via the through electrode 3 of the wiring circuit board 100, prevent the conductive layer 5 from being detached from the substrate 1, and provide a wiring circuit board 100 and the semiconductor device 200 having higher reliability
The present invention can be applied to a wiring circuit board provided between a package substrate and a semiconductor element, and to a semiconductor device provided with a wiring circuit board to be connected to a semiconductor element.
1: Base material
2: Electrolytic copper plating
3: Through electrode
4
a: Inorganic adhesive layer (first inorganic adhesive layer)
4
b: Inorganic adhesive layer (second inorganic adhesive Layer)
5
a: Conductive layer (first conductive layer)
5
b: Conductive layer (second conductive layer)
5
c: Conductive layer (second conductive layer)
6: Land
7: Insulative resin layer
8: Wiring group
9: Conductive via hole
10: Core substrate
11: Semiconductor element
12: Solder resist
13: Through hole
14: Filling resin
15: Conductive pad
100: Wiring circuit board
200: Semiconductor device
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-231842 | Nov 2014 | JP | national |
This application is a continuation application filed under 35 U.S.C. §111(a) claiming the benefit under 35 U.S.C. §§120 and 365(c) of International Application No. PCT/JP2015/005144, filed on Oct. 9, 2015, which is based upon and claims the benefit of priority of Japanese Patent Application No. 2014-231842, filed on Nov. 14, 2014, the entireties of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2015/005144 | Oct 2015 | US |
| Child | 15594396 | US |
