1. Field of the Invention
The present invention relates to a wiring substrate formed with a packaging substrate, a motherboard and a bonding member to connect them.
2. Description of Background Art
Japanese Laid-Open Patent Publication No. 2010-283056 describes packaging, and according to Japanese Laid-Open Patent Publication No. 2010-283056, a semiconductor element is mounted on one surface of the package, and the other surface is connected to a motherboard through external connection terminals such as solder balls. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a wiring substrate includes a motherboard having resin insulation layers, conductive layers and interlayer connection conductors connecting the conductive layers through the resin insulation layers, a packaging substrate mounted to the motherboard and having a core substrate including a resin substrate, through-hole conductors penetrating through the resin substrate, an uppermost interlayer resin insulation layer formed on a first surface of the resin substrate, pads formed on the first interlayer resin insulation layer and positioned to mount a semiconductor device, uppermost via conductors connecting the through-hole conductors and the pads for the semiconductor device through the uppermost interlayer resin insulation layer, a lowermost interlayer resin insulation layer formed on a second surface of the resin substrate, pads formed on the lowermost interlayer resin insulation layer and positioned to connect a motherboard, and lowermost via conductors connecting the through-hole conductors and the pads for the motherboard through the lowermost interlayer resin insulation layer, and bonding structures interposed between the motherboard and the packaging substrate and connecting the pads for the motherboard in the packaging substrate and an outermost conductive layer of the conductive layers in the motherboard facing the packaging substrate. The pads for the motherboard, the lowermost via conductors, the through-hole conductors, the uppermost via conductors, the bonding structures and the interlayer connection conductors include a pad, a lowermost via conductor, a through-hole conductor, a bonding structure and a stacked interlayer connection conductor structure which are positioned to align in a straight line.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
Wiring substrate 100 according to a first embodiment is described with reference to
Thickness (t2) of motherboard 110 is greater than thickness (t1) of packaging substrate 10. Thickness (t1) is set from 0.1 mm to 0.35 mm, and (t2) is set from 0.4 mm to 1.2 mm. When (t1) and (t2) satisfy the above relationship, heat tends to be transferred from the packaging substrate to the motherboard.
Solder-resist layers 180 with openings 181 are formed on uppermost and lowermost resin insulation layers (130U, 130L). Via conductors and conductive circuits exposed through the openings work as external terminals. Nickel layer 182 and gold layer 184 are formed on the external terminals. Bonding members (not shown in the drawings) such as solder bumps are formed on the external terminals, and a packaging substrate, an electronic component and a motherboard are connected through the bonding members. Since the motherboard has a full stacked-via structure, the conductor distance in a thickness direction is reduced, and wiring resistance decreases. Heat dissipation improves. The loss of electric power is suppressed. It is an option for bonding members for connection with a packaging substrate to be formed on the packaging substrate instead of being formed on the motherboard.
Upper buildup layers are formed on first surface (F) of core substrate 30. The upper buildup layers are made up of uppermost interlayer resin insulation layer (50U) formed on the first surface of the core substrate, pads (IP) which are formed on uppermost interlayer resin insulation layer (50U) and are for mounting a semiconductor element, and via conductors (uppermost via conductors) (59U) which penetrate through uppermost interlayer resin insulation layer (50U) and connect the pads for mounting a semiconductor element and the through-hole conductors.
Lower buildup layers are formed on second surface (S) of core substrate 30. The lower buildup layers are made up of lowermost interlayer resin insulation layer (50D) formed on the second surface of the core substrate, pads (MP) which are formed on lowermost interlayer resin insulation layer (50D) and are for connection with a motherboard, and via conductors (lowermost via conductors) (59D) which penetrate through lowermost interlayer resin insulation layer (50D) and connect the pads for connection with a motherboard and the through-hole conductors.
The packaging substrate has a full stacked-via structure the same as in the motherboard. The full stacked-via structure of the packaging substrate is formed with through-hole conductor 36 and via conductors (59U, 59D) sandwiching through-hole conductor 36. Through-hole conductor 36 and via conductors (59U, 59D) sandwiching the through-hole conductor are laminated along a straight line. A through-hole land is formed around the through-hole conductor. A through-hole land is a conductive circuit extending from the through-hole conductor and formed on the insulative base.
Via conductors in the packaging substrate also have tops and bottoms the same as the via conductors in the motherboard. Also, via-conductor openings have top and bottom diameters (
Upper solder-resist layer (80U) having openings 81 is formed on the upper buildup layers. The openings of the upper solder-resist layer expose the pads of the upper buildup layers. Lower solder-resist layer (80D) having openings 81 is formed on the lower buildup layers. The openings of the lower solder-resist layer expose the pads of the lower buildup layers. Nickel layer 82 and gold layer 84 are formed on pads (IP, MP). Solder bumps (86U) for mounting a semiconductor element are formed on the pads of the upper buildup layers. It is an option for bonding members (86D) such as solder bumps for connection with a motherboard to be formed on the pads of the lower buildup layers.
When the packaging substrate has a full stacked-via structure, the conductor distance is reduced in a thickness direction, and wiring resistance decreases. Heat dissipation improves. The loss of electric power is suppressed.
The motherboard and the packaging substrate are aligned, and they are bonded by solder bumps. Pads of the packaging substrate for connection with the motherboard and external terminals of the motherboard are connected by solder bumps. As shown in
Heat generated in the semiconductor element is transferred to a full stacked-via structure in the motherboard by way of a full stacked-via structure in the packaging substrate. Since heat is transferred in almost the minimum distance from the upper surface of the packaging substrate to the lower surface of the motherboard, heat generated in the semiconductor element does not build up in the packaging substrate, but is transferred to the motherboard. Heat dissipation improves.
The number of stacked structures that reach from the packaging substrate to the motherboard (total stacked structures) is preferred to be in a predetermined range.
There are multiple pads (MP) (M-pads) for connection with the motherboard. M-pads include multiple first pads. A first pad is part of a total stacked structure. Among the multiple M-pads, 1/5 (20%) to 1/2 (50%) of M-pads (first pads) are part of total stacked structures. For example, when the number of M-pads is 100, full stacked-via structures of the packaging substrate are formed on 20˜50 M-pads, and solder bumps and full stacked-via structures of the motherboard are formed directly under those full stacked-via structures of the packaging substrate. If the percentage of the total stacked structures is less than 20%, heat dissipation is not significantly improved. If the percentage of the total stacked structures exceeds 50%, heat dissipation declines. Without being bound by the theory, the reasons for that are thought to be that since efficiency in wiring design is lowered, the number of buildup layers in the packaging substrate increases, or the size of the packaging substrate enlarges.
The wiring substrate includes signal wiring, power-source wiring and ground wiring. Signal wiring is preferred to have low resistance to allow transmission of high-speed signals. Power-source wiring is preferred to have low resistance to allow instantaneous power supply for the semiconductor element. Therefore, it is not considered preferable to use signal or power-source wiring for heat dissipation, because heat causes an increase in wiring resistance. It is preferable to use ground wiring as the wiring for heat dissipation. Accordingly, a total stacked structure is preferred to be ground wiring. There are multiple ground pads (G-pads) for connection with the motherboard. Among the multiple G-pads, 1/5 (20%) to 1/2 (50%) of G-pads are part of total stacked structures. For example, when the number of G-pads is 100, full stacked-via structures of the packaging substrate are formed on 20-50 G-pads, and solder bumps and full stacked-via structures of the motherboard are formed directly under the full stacked-via structures of the packaging substrate. If the percentage of the total stacked structures is less than 20%, heat dissipation is not significantly improved. If the percentage of the total stacked structures exceeds 50%, heat dissipation declines. Without being bound by the theory, the reasons for that are thought to be that since efficiency in wiring design is lowered, the number of buildup layers in the packaging substrate increases, or the size of the packaging substrate enlarges.
Next, a method for manufacturing motherboard 110 is described with reference to
(1) Substrate (130A) is prepared, which is made up of resin insulation layer 130 and metal foils (132, 132) laminated on both surfaces of the resin insulation layer (
(2) A laser is irradiated on copper foil 132 formed on the first surface of the resin insulation layer so that openings for interlayer connection conductors (via-conductor openings) 133 are formed to reach copper foil 132 formed on the second surface of the resin insulation layer (
(3) Electrolytic plated films 135 are formed on electroless plated films on both surfaces. At the same time, via-conductor openings 133 are filled with electrolytic plated film 135 (
(4) Etching resists 139 are formed on electrolytic plated films 135 on both surfaces (
(5) Electrolytic plated film 135, electroless plated film 131 and metal foil 132 exposed from etching resists 139 are etched away (
(6) Prepreg and a metal foil are laminated in that order on both surfaces of the substrate shown in
(7) A laser is irradiated on copper foils (132, 132) which are laminated on the first and second surfaces of the resin insulation layer as the starting material with resin insulation layers in between. Openings (143A, 143B) for via conductors are formed in the resin insulation layers laminated on the first and second surfaces of the resin insulation layer as the starting material (
(8) Electrolytic plated films (145, 145) are formed on electroless plated films 141. Simultaneously, openings (143A, 143B) are filled with electrolytic plated films (145, 145) (
(9) Etching resists 149 are formed on electrolytic plated films (145, 145) (
(10) Electrolytic plated film 145, electroless plated film 141 and metal foil 132 exposed from etching resists 149 are etched away. Then, etching resists 149 are removed, and via conductors (146, 146) and conductive layers (147, 147) are formed (
(11) Steps (6)˜(10) above (steps in
(12) Solder-resist layers 180 having openings 181 are formed on both surfaces of the substrate shown in
(13) Nickel-plated layer 182 is formed on external terminals. Gold-plated layer 184 is formed (
In the following, a method for manufacturing packaging substrate 10 is described with reference to
(1) Substrate (30A) with metal foils is prepared, which is formed with resin substrate 300 and metal foils (32, 32) laminated on both surfaces of resin substrate 300 (
(2) Hourglass-shaped penetrating holes 33 for through-hole conductors are formed in resin substrate 300 (
(3) By performing an electrolytic plating process, electrolytic plated films (35, 35) are formed on electroless plated films 31. At this time, penetrating holes are filled with electrolytic plated film (
(4) Etching resists 37 are formed on the electrolytic plated films formed on the first and second surfaces of the resin substrate (
(5) Electrolytic plated film 35, electroless plated film 31 and copper foil 32 exposed from etching resists 37 are etched away. Then, etching resists 37 are removed and through-hole conductors 36 are formed. Simultaneously, conductive layers 34 are formed on the first and second surfaces of the resin substrate. Conductive layers 34 include through-hole lands (
(6) Resin film for interlayer resin insulation layers (brand name: ABF-45SH, made by Ajinomoto) and metal foil 520 are placed on both surfaces of core substrate 30. Then, thermal pressing is conducted and interlayer resin insulation layers (50U, 50D) and metal foils (520, 520) are formed on the core substrate (
(7) Next, using a CO2 gas laser, openings 51 for via conductors are formed in interlayer resin insulation layers (50U, 50D) (
(8) Electroless plated film 52 with a thickness of 0.1 μm to 2 μm is formed in openings 51 and on copper foils 520 (
(9) Plating resists 54 with a thickness of 15 μm to 20 μm are formed on electroless plated films 52 (
(10) Next, electrolytic plated films 56 with a thickness of 6 μm to 18 μm are formed on electroless plated films exposed from plating resists 54 (
(11) Plating resists 54 are removed. Then, electroless plated film 52 and metal foil 520 exposed from the electrolytic plated films are removed. Conductive layers (58U, 58D) and via conductors (59U, 59D) are formed (
The upper buildup layers are made up of uppermost interlayer resin insulation layer (50U) formed on the first surface of the core substrate (first surface of the resin substrate), uppermost conductive layer (58U) on the uppermost interlayer resin insulation layer, and uppermost via conductors (59U) which penetrate through the uppermost interlayer resin insulation layer and connect through-hole conductors 36 and uppermost conductive layer (58U). The uppermost conductive layer includes the C4 pads.
The lower buildup layers are made up of lowermost interlayer resin insulation layer (50D) formed on the second surface of the core substrate (second surface of the resin substrate), lowermost conductive layer (58D) on the lowermost interlayer resin insulation layer, and lowermost via conductors (59D) which penetrate through the lowermost interlayer resin insulation layer and connect through-hole conductors 36 and lowermost conductive layer (58D). The lowermost conductive layer includes the BGA pads.
(12) Solder-resist layers (80U, 80D) having openings 81 are formed on the upper and lower buildup layers (
(13) Next, metal film 84 is formed on pads (IP, MP) (
(14) Solder bumps (86U, 86D) are formed on pads (IP, MP) (
The connection of packaging substrate 10 and motherboard 110 is described.
Using alignment marks in the packaging substrate and alignment marks in the motherboard, pads (MP) of the packaging substrate and the external terminals of the motherboard are aligned. Then, the packaging substrate is mounted on the motherboard. After that, a reflow process is conducted to bond the packaging substrate and the motherboard. Wiring substrate 100 is completed. The uppermost resin insulation layer of the motherboard is the resin insulation layer closest to the packaging substrate, and the lowermost resin insulation layer is the resin insulation layer farthest from the packaging substrate.
Resin filler 188 may be filled between motherboard 110 and packaging substrate 10.
Next, semiconductor element 200 is mounted through solder bumps (86U), and underfill 288 is filled between semiconductor element 200 and packaging substrate 10. It is an option for a semiconductor element to be mounted on the packaging substrate, and then for the packaging substrate to be connected to the motherboard. The same materials may be used for resin filler 188 and underfill 288. In doing so, cracking is suppressed from occurring in solder bumps (86U) between the semiconductor element and the packaging substrate as well as in solder bumps (86D) between the packaging substrate and the motherboard.
In the second embodiment as well, heat generated in semiconductor element 200 is transferred from the packaging substrate to the motherboard by way of a distance close to the minimum distance.
In the first embodiment, in a modified example of the first embodiment, in another modified example of the first embodiment, and in the second embodiment and the third embodiment, since a semiconductor element is efficiently cooled, the semiconductor element is unlikely to malfunction, allowing it to operate for a long duration at maximum frequency.
A wiring substrate according to an embodiment of the present invention is formed with a motherboard, a packaging substrate, and a bonding member to connect the motherboard and the packaging substrate. The packaging substrate is formed with the following: a core substrate made up of a resin substrate having a first surface and a second surface opposite the first surface and of a through-hole conductor penetrating through the resin substrate; an uppermost interlayer resin insulation layer formed on the first surface of the resin substrate and on the through-hole conductor; a pad formed on the uppermost interlayer resin insulation layer for mounting a semiconductor element; an uppermost via conductor penetrating through the uppermost interlayer resin insulation layer and connecting the through-hole conductor and the pad for mounting a semiconductor element; a lowermost interlayer resin insulation layer formed on the second surface of the resin substrate and on the through-hole conductor; a pad formed on the lowermost interlayer resin insulation layer for connection with a motherboard; and a lowermost via conductor penetrating through the lowermost interlayer resin insulation layer and connecting the through-hole conductor and the pad for connection with a motherboard. The motherboard is formed with the following: multiple resin insulation layers and multiple conductive layers which are alternately laminated; and interlayer connection conductors penetrating through their respective resin insulation layers and connecting different conductive layers. In such a wiring substrate, pads for connection with a motherboard include multiple first pads, and the lowermost via conductor connected to a first pad, the through-hole conductor, the uppermost via conductor, the bonding member, and the interlayer connection conductor formed in each resin insulation layer of the motherboard are laminated along a straight line.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
The present application is based upon and claims the benefit of priority from U.S. Application No. 61/599,637, filed Feb. 16, 2012, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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61599637 | Feb 2012 | US |