Adhesive/spacer island structure for multiple die package

Abstract

An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.

Description

BACKGROUND

To obtain the maximum function and efficiency from the minimum package, various types of increased density packages have been developed. Among these various types of packages is the multiple-die semiconductor chip package, commonly referred to as a multi-chip module, multi-chip package or stacked chip package. A multi-chip package includes one or more integrated circuit semiconductor chips, often referred to as circuit die, stacked one onto another to provide the advantages of light weight, high density, and enhanced electrical performance. To stack the semiconductor chips, each chip can be lifted by a chip-bonding tool, which is usually mounted at the end of a pick-and-place device, and mounted onto the substrate or onto a semiconductor chip mounted previously.

In some circumstances, such as when the upper die is smaller than the lower die, the upper die can be attached directly to the lower die without the use of spacers. However, when spacers are needed between the upper and lower die, spacer die, that is die without circuitry, can be used between the upper and lower die. In addition, adhesives containing spacer elements, typically micro spheres, are often used to properly separate the upper and lower die. See U.S. Pat. Nos. 5,323,060; 6,333,562; 6,340,846; 6,388,313; 6,472,758; 6,569,709; 6,593,662; 6,441,496; and U.S. patent publication number U.S. 2003/0178710.

After the chip mounting process, bonding pads of the chips are connected to bonding pads of the substrate with Au or Al wires during a wire bonding process to create an array of semiconductor chip devices. Finally, the semiconductor chips and their associated wires connected to the substrate are encapsulated, typically using an epoxy-molding compound, to create an array of encapsulated semiconductor devices. The molding compound protects the semiconductor devices from the external environment, such as physical shock and humidity. After encapsulation, the encapsulated devices are separated, typically by sawing, into individual semiconductor chip packages.

SUMMARY

A first aspect of the invention is directed to an adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. The adhesive/spacer structure comprises a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation.

A second aspect of the invention is directed to multiple-die semiconductor chip package. A first die is mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate. A second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween. A plurality of spaced-apart adhesive/spacer islands are within the die bonding region and secure the first and second die to one another at a chosen separation to create a multiple-die subassembly. The adhesive/spacer islands comprise spacer elements within an adhesive. A material encapsulates the multiple-die subassembly to create a multiple-die semiconductor chip package.

A third aspect of the invention is directed to adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. The first and second die define a die bonding region therebetween. The adhesive/spacer structure comprises spacer elements within an adhesive. The adhesive/spacer structure secures the first and second die to one another and occupies at most about 50% of the die bonding region.

A fourth aspect of the invention is directed to a multiple-die semiconductor chip package. A first die is mounted to a substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate. A second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween. An adhesive/spacer structure within the die bonding region secures the first and second surfaces to one another at a chosen separation to create a multiple-die subassembly. The adhesive/spacer structure comprises spacer elements within an adhesive. The adhesive/spacer structure and occupies at most about 50% of the die bonding region. A material encapsulates the multiple-die subassembly to create a multiple-die semiconductor chip package.

A fifth aspect of the invention is directed to a method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. An adhesive/spacer material having spacer elements within an adhesive is selected. The adhesive/spacer material is deposited onto a first surface of a first die at a plurality of spaced-apart positions. A second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby securing the first and second die to one another at a chosen separation. The selecting and depositing steps are carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.

A sixth aspect of the invention is directed to a method for creating a multiple-die semiconductor chip package. A first die is mounted to a substrate, the first die having a first surface with bond pads at the first surface. The bond pads are connected to the substrate with wires. An adhesive/spacer material, comprising spacer elements within an adhesive, is selected. The adhesive/spacer material is deposited onto the first surface of the first die at a plurality of spaced-apart positions. A second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die subassembly. The selecting and depositing steps are carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step. The multiple-die subassembly is encapsulated to create a multiple-die semiconductor chip package.

A seventh aspect of the invention is directed to a method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. An adhesive/spacer material, having spacer elements within an adhesive, is selected. An amount of the adhesive/spacer material is chosen. The chosen amount the adhesive/spacer material is deposited onto a first surface of a first die. A second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation. The choosing and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step.

An eighth aspect of the invention is directed to a method for creating a multiple-die semiconductor chip package. A first die, comprising a first surface with bond pads at the first surface, is mounted to a substrate. The bond pads and the substrate are connected with wires. An adhesive/spacer material having spacer elements within an adhesive is selected. The adhesive/spacer material is deposited onto a first surface of the first die at a plurality of spaced-apart positions. A second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die subassembly. The selecting and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region. The multiple-die subassembly is encapsulated to create a multiple-die semiconductor chip package, with the encapsulating material occupying a second percentage of the die bonding region.

The present invention provides several potential advantages over conventional die stacking structure, specifically silicon spacer die and conventional spacer adhesives. The number of processing steps is reduced compared to conventional packages using silicon spacer wafers. According to the present invention, material processing can be simplified, the amount of spacer material used can be reduced and package reliability and productivity can be potentially increased.

Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are side views of conventional multiple die subassemblies using a spacer die and an adhesive/spacer material to separate the upper and lower die, respectively;

FIGS. 3-5 illustrate deposition of adhesive/spacer material onto a lower die using a shower head-type of dispenser;

FIG. 6 is a side view of a multiple-die subassembly made according to the invention following the deposition step of FIG. 5 and placement of an upper die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the upper die on and securing the upper die to the lower die;

FIG. 7 is a top view of the subassembly of FIG. 6 with the top die removed to illustrate the adhesive/spacer islands;

FIG. 8 illustrates an alternative embodiment of the structure shown in FIG. 7;

FIGS. 9-11 illustrate alternative embodiments of the lower die of FIG. 7 with adhesive/spacer islands having different sizes and shapes;

FIG. 12 illustrates a multiple-die semiconductor chip package made according to the invention by encapsulating the multiple-die subassembly of FIG. 6 with an encapsulating material;

FIGS. 13-15 illustrate continuous expanses of adhesive/spacer material instead of spaced-apart adhesive/spacer islands; and

FIG. 16 is a simplified plan view of a center bonded die with adhesive/spacer material applied thereto.

FIG. 17 is a side view of a multiple-die subassembly made according to the invention having a third die mounted upon the second die in a subassembly as in FIG. 6, following deposition of adhesive/spacer material as illustrated in FIG. 5 onto the second die, and placement of the third die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the third die on and securing the third die to the second die.

DETAILED DESCRIPTION

The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs.

Several prior art structures and embodiments made according to the invention are discussed below. Like reference numerals refer to like elements.

FIG. 1 illustrates a conventional multiple die subassembly 10 comprising a substrate 12 to which a first, lower die 14 is adhered using an adhesive 16. A second, upper die 18 is mounted to first die 14 by a spacer die 20, the spacer die being adhered to first and second die 14, 18 by adhesive layers 22, 24. Wires 26 connect bond pads 28, 30 of first and second die 14, 18 with bond pads 32 on substrate 12. FIG. 2 shows a conventional multiple die subassembly 34 similar to that of FIG. 1 but using a spacer/adhesive material 36 instead of spacer die 20 and adhesive layers 22, 24. Spacer/adhesive material 36 completely fills the die-bonding region 38 defined between first and second die 14, 18.

FIGS. 3-6 illustrate one procedure according to the invention for applying adhesive/spacer material 36 to a first die 14. In this embodiment a shower head-type dispenser 40 is used to apply material 36 at four spaced apart positions on first die 14. It is typically preferred to use a dot pattern type of shower head-type dispenser 40 instead of a conventional dispenser capillary because the one-step injection process can reduce dispensing time. Also, the amount and position for each deposit 42 can also be more easily controlled.

Each deposit 42 of material 36, see FIGS. 5-7, comprises adhesive 44 and at least one spacer element 46. Material 36 may be a conventional material such as Loctites QMI536-3, 4, 6, which uses nominal 3, 4 and 6 mil (75, 100 and 150 micrometers) diameter organic polymer spherical particles as spacer elements 46, or a spacer adhesive from the Ablestik 2025 Sx series. It is preferred that spacer elements 46 be an organic polymer material and pliable and large enough to accommodate wires 26 extending from bond pads 28 on, in this embodiment, first die 14. Spacer elements 46 are typically about 30-250 micrometers in diameter. Material 36 also helps to provide bond line thickness control and die tilt control. Examples of suitable materials for spacer elements 46 include PTFE and other polymers.

Spacer elements 46, prior to use, are typically spherical, ellipsoidal, cylindrical with hemispherical or ellipsoidal ends, or the like. After assembly, assuming spacer elements 46 are compressible, spacer elements 46 are compressed to some degree and have flattened areas where they contact lower and upper die 14, 18; the shape of such spacers is collectively referred to as generally ellipsoidal. For example, an initially spherical spacer element 46 having an 8 mil (200 micrometer) diameter will typically compress to a height of about 7.5 mil (188 micrometers). The height of spacers 46, which is equal to chosen separation 53, is usually at least equal to the wire loop height, is more usually greater than the wire loop height, and can be at least about 10% greater than the wire loop height, of wires 26 extending from bond pads 28 of first, lower die 14. If desired, the selection of the spacer elements includes selecting spacer elements so that chosen separation 53 is equal to a design wire loop height plus an allowance for manufacturing tolerance build-up resulting from making the wire bonds, the variance in the size and compressibility the of spacer elements 46 and other appropriate variables.

FIG. 8 illustrates an alternative embodiment in which dispenser 40 previously dispensed five spaced apart deposits 42 of material 36 onto first die 14. The number, size and position of deposits 42 will depend upon various factors including the size of the die and the package description.

Following the deposition of deposits 42, second, upper die 18, preferably having a dielectric layer 48 at its second, lower surface 50, is secured to first, lower die 14 by deposits 42 of material 36 to create a multiple-die subassembly 51 with upper and lower die 14, 18 separated by a chosen separation 53. See FIG. 6. This causes deposits 42 to spread out somewhat, see FIGS. 7 and 8, creating adhesive/spacer islands 52 spaced apart from one another. In the embodiment of FIGS. 3-8, each deposit 42 of material 36 creates a separate adhesive/spacer island 52; that is, none of the deposits 42 merge. In some situations certain of the deposits 42 of material 36 may merge while still creating a plurality of adhesive/spacer islands 52. See, for example, the adhesive/spacer islands 52A of FIGs. 9 and 10.

The dielectric layer 48 serves to prevent electrical shorting in the event of contact between the die 18 and the wire loops between it and the die 14 upon which it is mounted. This provides a significant advantage in manufacturing, according to the invention. Where no dielectric layer is provided on the underside of the upper die in a stack, the finished separation between the lower surface of the upper die and the upper surface of the lower die must necessarily be at least as great as the design wire loop height above the upper surface of the lower die. Because of variations in manufacture the specified separation must be made considerably greater than the design wire loop height; particularly, for example, some allowance must be made for variation in the actual heights of the loops, variation in the size of the spacer elements (particularly, variation in the height dimension of the compressed spacer elements). These allowances can result in significant addition to the separation in the finished stack and, therefore, these allowances can result significant increase in the overall thickness of the finished package. The effect is greater where a multiple die package includes more than two separated (spaced apart) stacked die.

In contrast, where the underside of the upper die in a stacked pair of die according to the invention is provided with a dielectric layer, the allowance may be considerably reduced. Although it may not be particularly desirable for the wire loops to contact the underside of the upper die (that is, to contact dielectric layer), it is not fatal to the package if contact sometimes results during manufacture and, accordingly, it is not necessary to add significantly to the separation specification or to the resulting package height.

The multiple spacer island embodiments of FIGS. 6-11 may be designed so that each of the adhesive/spacer islands 52 is the same size, such as in FIGS. 6 and 7, or of different sizes, such as adhesive/spacer islands 52A in FIGS. 9-11. Adhesive/spacer islands 52, 52A occupy only a percentage of die bonding region 38, preferably at most about 50% and more preferably about 20-50 percent of die bonding region 38. Thereafter, an encapsulating material 54 is used to create a multiple-die semiconductor chip package 56 as shown in FIG. 12. The encapsulating process typically occurs under a vacuum so that encapsulating material 54 also effectively fills the open regions between islands 52, 52A so that encapsulating material 54, wires 26 and islands 52 occupied about 100% of die bonding region 38 therefore effectively eliminating voids within the die bonding region.

Encapsulating material 54 may be a conventional material comprising a filled epoxy; filled epoxy materials typically comprise about 80-90 percent small, hard filler material, typically 5-10 micrometer glass or ceramic particles. Therefore, conventional encapsulating material 54 would not be suitable for use as adhesive 58 because the small, hard filler material could be captured between spacer element 46 and either or both of die 14, 18, resulting in damage to the die. Boundaries 58 are created between adhesive/spacer islands 52 and encapsulating material 54.

In some situations the plurality of spaced-apart adhesive/spacer islands 52, 52A may be replaced by a continuous expanses 60 of adhesive/spacer material 36 such as illustrated in FIGS. 13-15. Continuous expanse 60 of material 36 may be deposited so that it preferably occupies at most about 50% of die bonding region 38, and more preferably about 20-50% of die bonding region 38.

The present invention finds particular utility for use with a center bonded die 64, see FIG. 16, such as a DRAM, having peripheral edges 68-71 and having bond pads 28 at a central region 66 of die 64. Wires 26 extending from bond pads 28 extend past peripheral edges 68, 70. The distance between the bond pads and the corresponding peripheral edges for a center bonded die is preferably much more than 100 micrometers. More preferably, the distance between a bond pad 28 for a center bonded die 64 and the nearest peripheral edge is at least about 40% of the corresponding length or width of the die. For example, the distance between a bond pad 28A and peripheral edge 68 is at least about 40% of the length of peripheral edge 69. Assuming peripheral edge 69 is 8 mm long, the distance between bond pad 68A and peripheral edge 68 is at least about 3.2 mm.

The multiple die packages illustrated by way of example in FIG. 12 have two die in the stack, a first die and a second die. Multiple die packages according to the invention may have three or more die in the stack. A multiple die stack having three stacked die, for example, can be made by providing a multiple-die assembly as in FIG. 6, and mounting an additional die upon the second die by depositing adhesive/spacer material onto the second die generally as shown in FIG. 5 and placing the third die onto the deposits to make a three-die assembly as shown generally at 172 in FIG. 17. Referring to FIG. 17, a two die assembly as in FIG. 6 has a die 18 stacked over a die 14, which is mounted onto a substrate 12 using an adhesive (in this instance, adhesive spots are used to attach the die 14 to the substrate 12). The die 18 is separated from the die 14 by adhesive/spacer islands 52, each including adhesive 44 and at least one spacer element 46. A dielectric layer 48 applied onto the lower surface 50 of the die 18 serves to prevent electrical shorting between the die 18 and wire bonds interconnecting the die 14 and the substrate 12, and thereby allows for reduction of tolerances for the spacer dimension, as described above. Interconnection of the die 18 with the substrate 12 is made by wire bonds 26 connected to bond pads 30 on die 18. To mount an additional die 78, deposits of adhesive/spacer material, including adhesive 74 and at least one spacer element 76, are applied on the surface of die 18, generally as described above with reference to FIGS. 3-5, and then die 78, having a dielectric layer 88 applied onto the lower surface 170, is placed upon the adhesive/spacer material deposits. The resulting adhesive/spacer islands 72 provide a sufficient between the die 78 and the die 18 equal to a design wire loop height for wire bonds 26 plus an allowance for manufacturing tolerance. Electrical interconnect between the die 78 and the substrate is then made, using a wire bonding tool to connect to bond pads 80. According to the invention, further additional die can be added to the stack. When the stack is complete, an encapsulating process is employed to complete the package and, where the package is made in an array of packages on a multipackage substrate, the packages are separated from one another by saw- or punch-singulation.

The adhesive/spacer structures are shown in FIGS. 6 and 17 as constituting islands having regular size and shape; according to the invention the islands may have any of various shapes and sizes, as described above with reference, for example, to FIGS. 9-11 and 13-16.

In multiple die packages according to the invention, at least two die in the stack are separated by an adhesive/spacer structure; or, at least the lower die in the stack is separated from the substrate by a adhesive/spacer structure. All the die may be separated by spacers, at least two of them being separated by a adhesive/spacer structure; or, in some instances where one or more die is narrower than the die upon which it is stacked, no spacer may be required between those two die.

Other modification and variation can be made to the disclosed embodiments without departing from the subject of the invention as defined in the following claims. For example, although the above embodiments disclose the use of adhesive/spacer material 36 between lower and upper die 14, 18, material 36 may also be used with multiple die semiconductor chip packages having, for example, four die with material 36 used between one, two or three of the pairs of adjacent die. Also, although the above described embodiments show the bump reverse bonding method for attaching wires 26 to bond pads 28, 30, the conventional forward wire bonding method can also be used.

Any and all patents, patent applications and printed publications referred to above are incorporated by reference.

Other embodiments are within the scope of the invention.

Claims

1. An adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the adhesive/spacer structure comprising: a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation; and said adhesive/spacer islands comprising an adhesive/spacer material, said adhesive/spacer material comprising deformable spacer elements embedded within adhesive.

2. The structure according to claim 1 comprising at least three of said spaced-apart adhesive/spacer islands.

3. The structure according to claim 1 wherein at least one of said adhesive/spacer islands comprises a plurality of said spacer elements.

4. The structure according to claim 1 wherein the spacer elements are all substantially the same size.

5. The structure according to claim 1 wherein the spacer elements comprise generally ellipsoidal spacer elements.

6. The structure according to claim 5 wherein the generally ellipsoidal spacer elements comprise flattened generally spherical spacer elements.

7. The structure according to claim 1 wherein the spacer elements are deformable polymer spacer elements.

8. The structure according to claim 7 wherein the deformable polymer spacer elements comprise PTFE.

9. The structure according to claim 1 wherein each of the adhesive/spacer islands are about the same size.

10. The structure according to claim 1 wherein a first of the adhesive/spacer islands is at least twice the size of a second of the adhesive/spacer islands.

11. A multiple-die semiconductor chip package comprising: a substrate; a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery to the substrate; a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer; a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple-die subassembly, the adhesive/spacer islands occupying a first percentage of the die bonding region; the adhesive/spacer islands comprising at least one spacer element within an adhesive; and a material encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.

12. The package according to claim 11 wherein the first percentage is between about 20-50 percent.

13. The package according to claim 11 wherein the first percentage is at most about 50%.

14. The package according to claim 11 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100 percent thereby effectively eliminating voids within the die bonding region.

15. The package according to claim 11 wherein: the adhesive comprises epoxy; and the encapsulating material comprises a filled epoxy.

16. The package according to claim 11 wherein the adhesive and the encapsulating material create an adhesive/encapsulating material boundary within the die bonding region.

17. An adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the multiple-die semiconductor chip package comprising the first and second die defining a die bonding region therebetween, the adhesive/spacer structure comprising: adhesive/spacer structure comprising spacer elements within an adhesive, the spacer elements comprising a deformable material; and the adhesive/spacer structure securing the first and second die to one another and occupying at most about 50% of the die bonding region.

18. The structure according to claim 17 wherein the adhesive/spacer structure comprises first and second adhesive/spacer structures spaced apart from one another.

19. The structure according to claim 17 wherein the adhesive/spacer structure comprises at least three adhesive/spacer structures spaced apart from one another.

20. The structure according to claim 17 wherein the adhesive/spacer structure occupies about 20-50% of the die bonding region.

21. A multiple-die semiconductor chip package comprising: a substrate; a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery to the substrate; a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer; adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die subassembly; the adhesive/spacer structure comprising spacer elements within an adhesive; the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%; and a material encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.

22. The package according to claim 21 wherein the first percentage is about 20-50%.

23. The package according to claim 21 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.

24. A method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: selecting an adhesive/spacer material having spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of a first die at a plurality of spaced-apart positions; providing a second surface of the second die with a dielectric layer; locating the second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: securing the first and second die to one another at a chosen separation; and the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.

25. The method according to claim 24 wherein the selecting step comprises choosing spacer elements having the same size and shape.

26. The method according to claim 24 wherein the depositing step is carried out to create a plurality of generally equal-size islands of the adhesive/spacer material after the securing step.

27. The method according to claim 24 wherein the depositing step is carried out to create at least three generally equal-size islands of the adhesive/spacer material after the securing step.

28. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die having a first surface with bond pads at the first surface; connecting the bond pads and the substrate with wires; selecting an adhesive/spacer material comprising spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions; providing a second surface of the second die with a dielectric layer; locating a second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation to create a multiple-die subassembly; the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step, the adhesive/spacer islands occupying a first percentage of the die bonding region; and encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.

29. The method according to claim 28 wherein the depositing step is carried out so that the first percentage is about 20-50 percent.

30. The method according to claim 28 wherein the depositing step is carried out so that the first percentage is at most about 50%.

31. The method according to claim 28 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.

32. A method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: selecting an adhesive/spacer material having spacer elements within an adhesive; choosing an amount of the adhesive/spacer material; depositing the chosen amount the adhesive/spacer material onto a first surface of a first die; providing a second surface of the second die with a dielectric layer; locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation; and the choosing and depositing steps carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step.

33. The method according to claim 32 wherein the depositing step is carried out to create a single, continuous expanse of the adhesive/spacer material after the securing step.

34. The method according to claim 32 wherein the choosing step is carried out so that the adhesive/spacer material occupies about 20-50% of the die bonding region.

35. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die comprising a first surface with bond pads at the first surface; connecting the bond pads and the substrate with wires; selecting an adhesive/spacer material having spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions; locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation to create a multiple-die subassembly; the selecting and depositing steps carried out so that the adhesive/spacer material occupies a first percentage of the die bonding region, the first percentage being at most about 50%; and encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.

36. The method according to claim 35 wherein the depositing step is carried out so that the first percentage is about 20-50%.

37. The method according to claim 35 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.