Patent Application
20070279885
In the Figures and text, like reference numerals indicate elements with similar functions.
In some Figures, relative dimensions of one or more features and/or structures may be exaggerated to more clearly show one or more of the features and/or structures being illustrated.
Herein, various embodiments are described more fully by the Figures and the Detailed Description of Illustrative Embodiments. Nevertheless, the inventions may be embodied in various forms and are not limited to the embodiments described in the Figures and Detailed Description of Illustrative Embodiments.
Various embodiments include packaged micro-electronic devices with electrical feedthroughs that traverse joints between the different parts of the packages. Herein, an electrical feedthrough is an electrical pathway that connects an electrical device inside the package to the exterior of the package.
The substrate 12, housing 16, and a joint 18 may form a hermetic package with a cavity 20 in which the micro-electronic structure 14 is located. In such embodiments, the joint 18 hermetically seals the cavity 20 enclosed between the substrate 12 and the housing 16. Such a hermetic package may maintain a partial vacuum in the cavity 20 or may maintain an inert gas such as nitrogen or argon at standard pressure in the cavity 20. In such embodiments, the substrate 12 has a physical composition suitable to function as a sealing wall of a hermetic package. Exemplary substrates 12 include crystalline semiconductor substrates, e.g., part of a wafer-substrate such as a silicon wafer-substrate.
The micro-electronic structure 14 is a device that performs a function that involves the transmission of electrical signals from the device and/or the receipt of electrical signals at the device. In particular, the micro-electronic structure 14 has conducting pads/connection points 22 that connect to conducting leads 24i internal to the cavity 20. The conducting leads 24i form parts of the conducting pathways for carrying electrical signals between the micro-electronic structure 14 and conducting leads 24e that connect to the exterior of the hermetic package.
The micro-electronic structure 14 may have a variety of forms. Exemplary micro-electronic structures 14 include an integrated micro-electronic circuit that processes electrical signals received from the exterior and/or transmits processed electrical signals to the exterior. Other exemplary micro-electronic structures 14 include one or more micro-electro-mechanical systems (MEMSs) that receive electrical control signals from the exterior. Some exemplary micro-electronic structures 14 are two-dimensional (2D) array-type devices. Examples of 2D array-type devices include 2D arrays of MEMS-controlled optical elements, e.g., adaptive optical 2D mirror or lens arrays, 2D arrays of vertical cavity surface emitting lasers (VCSELs), and 2D arrays of sensors, e.g., light-sensitive diode sensors. In such exemplary micro-electronic structures 14, the housing 16 is configured so that a window 26 passes visible or infrared light between the 2D array of optical elements and the exterior to the package.
The micro-electronic structure 14 may be susceptible to being physically damaged or to having its performance reduced when exposed to ambient environmental conditions. For example, exposure to ambient air or moisture may cause damaging corrosion to the micro-electronic structure 14. Also, exposure to air may cause unacceptable damping of mechanical motion during operation. As an example, the micro-electronic structure 14 may include a movable MEMS structure whose motion would be significantly and undesirably impacted by the presence of a gas at standard pressure. In such embodiments, to avoid such physical damage and/or performance reduction, the package maintains an environment that isolates the micro-electronic structure 14 from ambient external gases.
The micro-electronic structure 14 may also be integrated onto the substrate 12 or may be formed on one or more separate substrates that are mechanically fixed to the substrate 12.
The housing 16 may have a composition suitable to function as a sealing wall of a hermetic package, e.g., a composition impenetrable to ordinary gases. Exemplary housings 16 are made of metal, glass, ceramic, silicon, or a combination of such materials. Some embodiments of the housing 15 may include one or more silica glass windows 26 as already described.
The joint 18 may have a composition suitable to function as part of a sealing wall of a hermetic package. In such embodiments, the sealing joint 18 forms a hermetic seal along the boundary region between the housing 16 and the substrate 12. The joint 18 also includes portions of the electrical feedthroughs that provide electrical connections between the micro-electronic structure 14 and the exterior of the package.
The joint 18 includes an inorganic dielectric layer 28, a metallic layer 30, an inorganic dielectric capping layer 32, a sealing ring 34, and a top joint material 36.
The inorganic dielectric layer 28 is, e.g., a layer of silicon oxide and/or silicon nitride that is formed on a top surface of the substrate 12. The inorganic dielectric layer 28 may be, e.g., a layer of silicon dioxide that was grown on a portion of a silicon wafer substrate 12 and may have, e.g., a thickness of about 2 micrometers (μm) to about 5 μm. An underlying portion of the dielectric layer 28, e.g., one or more micrometers of the same dielectric, may electrically insulate the metallic layer 30 from the substrate 12. In the various embodiments, the thickness of the underlying portion of the dielectric layer 28 is selected as appropriate for the types of the electrical signals carried on the electrical feedthroughs.
In some embodiments, a different inorganic dielectric layer (not shown) underlies the inorganic dielectric layer 28 and electrically insulates the electrical feedthroughs from the underlying substrate 12, e.g., a semiconductor substrate.
The metallic layer 30 is made of separated elongated portions, which are located in trenches in the dielectric layer 28. The elongated portions preferably do not substantially overflow the trenches in which they are located and preferably substantially fill said trenches. Each separate elongated portion is a segment of one of the electrical feedthroughs that traverses the joint 18. Exemplary conducting layers 30 are formed of a metal such as gold (Au), copper (Cu), aluminum (Al), tungsten (W) or are formed of a metal multilayer. Such exemplary conducting layers 30 may or may not include an adhesion layer (e.g., a Ti or Cr adhesion layer).
The dielectric capping layer 32 is a conformal layer of inorganic dielectric that electrically insulates and protects the metallic layer 30 from corrosion and damage, i.e., a passifying layer. The dielectric capping layer 32 may be formed, e.g., of silicon dioxide and/or silicon nitride and may have, e.g., a thickness of about 1 μm to about 5 μm.
The sealing ring 34 has a composition that can bond to the top joint material 36 and to the dielectric capping layer 32. In particular, the bonding may enable, e.g., the formation of a hermetic seal.
The top joint material 36 fills the entire length and width of the physical gap between the housing 16 and the sealing ring 34 and bonds to both. For a metallic housing 16, an exemplary top joint material 36 is a conventional metallic solder. For such a top joint material 36, one suitable sealing ring 34 would be metal layers or multilayers, e.g., Ti/Pt/Au, Ti/Ni/Au, Cr/Cu/Au, etc.
In other embodiments (not shown), conducting pads on the bottom surface of the micro-electronic structure 14 connect the micro-electronic structure 14 to the elongated portions of the metallic layer 30 rather than wire bonds. That is, the micro-electronic structure 14 connects to the electrical feedthroughs via solder balls in a flip-chip configuration.
The view of the exemplary silicon wafer-substrate 12 of
One method for packaging a micro-electronic structure includes the steps of forming electrical portions of electrical feedthroughs on a flat portion of a first part of the package, depositing a layer of dielectric on the portions of the electrical feedthroughs, planarizing the layer of dielectric, and joining together the first and second parts of the package. Such a method produces a package in which electrical pathways traverse the joint between the parts of the package. Unfortunately, such a method may produce a joint that has small gaps therein, because blanket deposition of dielectric often does not completely fill spaces between neighboring portions of electrical feedthroughs. Such gaps are potential paths for gas leakage and can thus, be an obstacle to producing a hermetically sealed package. Furthermore, such gaps may be difficult to avoid as height-to-width aspect ratios of the electrical feedthroughs increase and/or as spacings between neighboring electrical feedthroughs decrease. Indeed, it may be desirable to reduce the spacing between neighboring electrical feedthroughs to increase their densities and/or to increase the height-to-width ratios of electrical feedthroughs to decrease their resistances. Thus, the above-described packaging method may be problematic in some applications of hermetic packages.
To produce hermetic packages with high electrical feedthrough densities and/or high height-to-width ratios of electrical feedthroughs, some embodiments of the below-described fabrication methods make portions of the electrical feedthroughs differently. In particular, these other methods form portions of the electrical feedthroughs in trenches in a layer of dielectric rather than forming the electrical feedthroughs on a planar surface and then, covering the electrical feedthroughs with a layer of dielectric. For that reason, the packages formed by the below-described methods may be less likely to have empty gaps between the electrical feedthroughs and thus, be less likely to have gas leaks in their sealing joints. These other methods may be performed as illustrated in
The method 40 includes forming an inorganic dielectric layer on the planar top surface of a semiconductor substrate, e.g., the dielectric layer 28 on the semiconductor substrate 12 (step 42). In an exemplary embodiment where the semiconductor substrate is a portion of a silicon wafer, the dielectric layer may be, e.g., a grown silicon oxide layer. The silicon oxide layer may be grown by exposing the surface of the silicon wafer to oxygen and water vapor at high temperature, e.g., about 1,000° Centigrade (C). The inorganic dielectric layer may also be a silicon dioxide or silicon nitride, which is formed, e.g., on the surface of the semiconductor wafer by conventional deposition methods known to those of skill in art.
The method 40 includes forming a patterned photoresist mask on the dielectric layer and then, etching an array trenches in the in the dielectric layer under control of the photoresist mask (step 44). The photoresist mask has an array of elongated windows whose sizes and locations correspond to the trenches desired for the electrical feedthroughs that will electrically connect the micro-electronic structure to the exterior.
A conventional lithographic patterning process may produce the photoresist mask. The etching step may include performing a plasma etch based on a conventional fluorine etching chemistry. The etch may be stopped before the trenches traverse the inorganic dielectric layer so that a suitable amount of same dielectric will remain to electrically insulate the final electrical feedthroughs from an underlying semiconducting substrate, e.g., a silicon wafer-substrate. Rather than stopping the etch prior to traversing the first dielectric layer, a second layer of the same or a different dielectric may be formed on the semiconductor substrate prior to step 42. Then, the second layer will electrically insulate the electrical feedthroughs from the semiconductor substrate.
The method 40 includes depositing metal in the trenches under control of the same photoresist mask (step 46). The metal deposition may involve, e.g., performing a conventional evaporation-deposition, e.g., a deposition of gold. The deposition step stops when the trenches are substantially filled so that the metal and the inorganic dielectric layer have surfaces of about the same height. The metal-filled trenches will form buried portions of electrical feedthroughs, e.g., of the conducting layer 30. The metal-filled trenches will electrically connect the micro-electronic structure being packaged to the exterior of the final package.
The method 40 includes washing the metallized surface of the intermediate structure, which was produced at step 46, with a solvent to remove the photoresist mask (step 48). The solvent-wash also lifts off excess metal that is located on the photoresist mask, e.g. to produce the electrical feedthroughs of the metallic layer 30. After the washing step, the surface of the inorganic dielectric layer and the metal-filled trenches may be flat enough so that a planarization is unnecessary provided that the deposition of metal substantially filled the trenches. The washing step also includes drying the washed structure.
The method 40 includes depositing a layer of inorganic dielectric, e.g., the capping dielectric layer 32, on the surface produced by the liftoff of step 48 (step 50). The inorganic dielectric may be, e.g., silicon oxide and/or silicon nitride and may have a thickness in the range of about 1 μm to 5 μm. Nevertheless, thinner or thicker layers of inorganic dielectric may be used as appropriate for the types of electrical signals that will be sent through the feedthroughs, e.g., as appropriate for the voltages and frequencies of said electrical signals. The deposition step includes, e.g., performing a chemical vapor deposition (CVD) or a sputtering deposition of the inorganic dielectric. The deposition step produces, e.g., a smooth capping layer of the inorganic dielectric on the underlying dielectric layer and metal-filled trenches therein. The capping layer electrically insulates the buried portions of the metal feedthroughs from later deposited materials and may protect said buried portions from corrosion and/or mechanical damage.
The method 40 may include forming a sealing ring, e.g., the sealing ring 34, on the capping dielectric layer along the region for the planned position of the joint between the semiconductor substrate and the housing (step 52). The sealing ring may be formed, e.g., by a shadow mask-controlled deposition so that material of the ring is selectively deposited along the planned position of the sealing joint. The sealing ring made of a material that is compatible with the material that will join the housing and substrate. If a conventional metal-alloy solder is planned for joining the housing and substrate, the sealing ring may be formed from metal multi-layers, e.g., Ti/Pt/Au, Ti/Ni/Au, or Cr/Cu/Au metal multi-layers.
The method 40 includes removing dielectric over the ends of the buried portions of the electrical feedthroughs (step 54). The removal step may include performing a conventional etch under the control of another photoresist mask. The removal step exposes an electrical connection pad at each end of the buried portions of the electrical feedthroughs.
The order of steps 52 and 54 may be inverted in other embodiments of methods for hermetically packaging a micro-electronics device.
The method 40 includes mounting the micro-electronic structure to be packaged, e.g., the micro-electronic structure 14, at the interior of the sealing ring on the surface of the substrate (step 56). The mounting step may include, e.g., gluing the micro-electronic structure onto the surface of the semiconductor substrate. The mounting step includes aligning the micro-electronic structure so that its connection pads are aligned with the electrical connection pads of the buried portions of the electrical feedthroughs.
In alternate embodiments, the mounting of the micro-electronic structure on the semiconductor substrate may be performed at an earlier stage in the packaging method.
In other alternate embodiments, the micro-electronic structure may be incorporated into the semiconductor substrate itself.
The method 40 includes electrically bonding the micro-electronics structure to the electrical feedthroughs (step 58). The step 58 of electrically bonding may involve wire bonding connection pads on the micro-electronic structure to the connection pads for the buried portions of the electrical feedthroughs. The wire bonding may involve, e.g., forming the wire bonds of Au wires, e.g., 1 mil Au wire bonds, using a model 8098 wire bonder, which is manufactured by Kulicke & Soffa Industries of Fort Washington, Pa. In some embodiments, the wire bonds (WBs) are tiered and connection pads are arranged in multiple rows so that the different tiers of wire bonds connect between different rows of the internal and external connection pads, i.e., the ICPs and ECPs. For example,
The method 40 includes positioning the housing over the sealing ring and sealing the housing to the semiconductor substrate with a joint material, e.g., the top joint material 36, to complete the package's hermetic sealing joint, e.g., sealing joint 18 of
After performing the sealing step, the hermetically packaged micro-electronic device may be stored, transported, or installed as desired. Prior to operation, electrical lines are connected to the exposed external ends of the electrical feedthroughs. These electrical lines may be made by the wire bonding processes already described with respect to the above step 58.
The packaging method 40 of
Since there is an inherent mismatch between the thermal expansivity of dielectrics and conductors, temperature variations can cause delaminations at the interfaces between electrical feedthroughs and dielectrics in the packaged micro-electronic devices 10 of
The sealing joint 18′ includes inorganic dielectric layer 28′, conducting layer 30′, dielectric layer 32′, sealing ring 34′, and joint material 36′. The elements 28′, 30′, 32′, 34′, and 36′ of the sealing joint 18′ have functions and compositions that are similar to those of respective elements 28, 30, 32, 34, 36, and 18 of
In the sealing joint 18′, the conducting layer 30′ may have a thermal coefficient of expansion that better matches to the thermal coefficients of expansion of the dielectric layers 28′, 32′. For example, tungsten (W) and heavily doped semiconductor have thermal expansions that better match those of surrounding dielectrics than gold. A better match between the thermal coefficients of expansion can reduce the potential for catastrophic delaminations between the layers 28′ and 30′ and between the layers 30′ and 32′ thereby lower the risk of hermeticity ruptures for the packaged micro-electronic device 10′. However, conductors with lower thermal expansions may also have lower electrical conductivity than metals like gold. The associated downside of having lower electrical conductivities can be partially offset by making buried portions of the electrical feedthroughs in the conducting layer 30′ shorter and/or by increasing the cross-sectional area of said buried portions, e.g., by increasing the height-to-width aspect ratio of the buried portions of the electrical feedthroughs.
In the sealing joint 18′, the buried portions of the electrical feedthroughs may also have dimensions that reduce stresses caused by temperature variations. For example, the individual elongated portions of the conducting layer 30′ may have a smaller cross-sectional areas than the individual elongated portions of the conducting layer 30 of
Also, in the sealing joint 18′, the individual elongated portions of the conducting layer 30′ may have circumferences that are smaller than the circumferences of the corresponding elongated portions of the conducting layer 30 of
The sealing joint 18′ also includes a top conducting layer 64, metal filled vias 66, a top inorganic dielectric layer 68, a sealing ring 34′, and joint material 36′. The top conducting layer 64 provides electrical connections between the individual buried elongated portions of the electrical feedthroughs of the conducting layer 30′ and the internal and external leads 24i, 24e. The top conducting layer 64 may be formed of materials of higher conductivity than the material of the conducting layer 30′, because delaminations of the conducting layer 64 do not necessarily cause ruptures of the hermeticity of the package. Exemplary materials for the top conducting layer 64 may include metals such as gold, aluminum, or copper. The metal filled vias 66 electrical connect the buried portions of the electrical feedthroughs in the conducting layer 30′ to the segments the top conducting layer 64. The vias 66 may be filled with metals, e.g., tungsten. The inorganic dielectric layer 68 may form part of the sealing joint 18′ and may provide additional electrical insulation between the conducting layer 30′ and the sealing ring 34′ and joint material 36′, which may be a metal-alloy solder.
The method 70 includes performing the steps 42, 44, 46, and 48 substantially as described with respect to method 40 of
As above, the buried portions of the electrical feedthroughs may have a density of at least 10 per millimeter (mm), and the density may be 50 or more per mm and may even be as high as 100-120 or more per mm. Also, the buried portions of the electrical feedthroughs may have heights normal to the top surface of the substrate of at least 0.5 μm and may even have heights of 1.0 μm or more, e.g., heights of 1.0 μm to 4.0 μm.
Next, the method 70 includes forming a second inorganic dielectric layer, e.g., the dielectric layer 32′, on the dielectric layer in which the conductor-filled trenches are located (step 72). The second dielectric layer may be, e.g., a conventionally deposited silicon dioxide and/or a silicon nitride layer. The second inorganic dielectric layer may have a thickness of about 1 μm to about 5 μm. The appropriate thickness of the second inorganic dielectric depends on the nature of electrical signals that will be carried by the electrical feedthroughs.
The method 70 includes forming a photoresist mask on the second dielectric layer (step 74). The photoresist mask may be formed by a variety of conventional processes known to those of skill in the art, e.g., lithographically patterning. The photoresist mask has windows for the locations of vias that will electrically connect ends of buried portions of the electrical feedthroughs of the first conducting layer, e.g., the vias 66 of
The method 70 includes dry or wet etching the second dielectric layer under the control of the photoresist mask (step 76). The dry or wet etching step produces the vertical vias. One via connects to each end of the buried portion of an electrical feedthrough of the first conducting layer.
The method 70 includes depositing metal under control of the same photoresist mask so as to fill the vias in the second dielectric layer (step 78). The deposition may involve an evaporation-deposition of titanium, gold, tungsten, or another metal, e.g., to form W or Ti/W plugs.
The method 70 includes washing the metallized surface of the intermediate structure from step 78 with a solvent to remove the photoresist mask (step 80). The solvent-wash also lifts off metal that overflows boundaries of the vias. After the solvent-wash, metal-filled vias remain, and the metal-filled vias connect to the ends of the buried portions of the electrical feedthroughs. The solvent-wash may include a step of drying the resulting intermediate structure.
Next, the method 70 includes forming a top metal layer, e.g., the top conducting layer 64, on the second dielectric layer (step 82). The top metal layer consists of connection pads and connection lines that link to the metal-filled vias. That is, one connection line and pad of the top metal layer connects to each end of the buried part of an electrical feedthrough of the first conducting layer via the metal-filled vias. One set of the connection lines and pads of the top metal layer will be external to the final package, and a second set of the connection lines and pads of the top metal layer will be internal to the final package. The top metal layer may be formed by two alternative processes.
The first process produces the top metal layer on the surface of the second dielectric layer. The first process includes performing an evaporation deposition of metal onto the top surface of the second dielectric layer under the control of another photoresist mask. The first process also includes performing a solvent-wash to remove the photoresist mask and to lift off excess metal, which is located on the photoresist mask. The resulting intermediate structure is then dried.
The second process produces a buried top metal layer on the top surface of the second dielectric layer. The second process includes depositing a third dielectric layer on the second dielectric layer, e.g., a silicon dioxide or silicon nitride. The second process includes forming a lithographically patterned photoresist mask on the third dielectric layer and then, etching the third dielectric layer to produce an array of trenches through the third dielectric layer. The second process also includes performing an evaporation deposition of metal on the third dielectric layer without removing the photoresist mask. The second process also includes performing a solvent-wash of the resulting intermediate structure to remove the photoresist mask and to lift off excess metal that is located on the photoresist. The second process also includes drying the resulting intermediate structure. The second process may exploit techniques similar to those of above-described steps 72, 74, 76, and 80.
The first process may be preferable to the second process where a thin top metal layer is desired, because a thin blanket dielectric coating may provide sufficient passivation or protective coverage of the electrical connection paths of such a thin top metal layer.
The first process may also be preferable to the second process where the top metal layer is thick and would produce stresses that interfere with a buried construction.
The second process may also be preferable to the first process if high reliability against breaches of hermeticity are desired. In particular, the second process produces a structure that is less likely to enable gas to leak in or out. For example, burying the top conducting layer may lower the risk of delaminations by the last dielectric layer.
The method 70 may include depositing a third inorganic dielectric layer, e.g., the dielectric layer 68, over the same surface of the structure (step 84). The third inorganic dielectric layer may function as a passivating layer for the top metal layer. The third inorganic dielectric layer may be, e.g., a silicon dioxide and/or silicon nitride and may have, e.g., a thickness in the range of 0.5 to 1 μm. or more. The third inorganic dielectric layer may be deposited by one of the above-described processes for depositing inorganic dielectric or may be deposited by other processes known to those of skill in the art.
The method 70 may also include forming a sealing ring, e.g., the sealing ring 34′, on the top dielectric layer along a planned joint region thereof (step 86). The formation of the sealing ring may involve performing a conventional deposition process under control of a shadow mask. The sealing ring is formed of a material suitable for bonding to a selected top joint material. When a conventional metal solder is planned for the top joint material, the sealing ring may be, e.g., Ti/Ni/Au, Ti/Pt/Au, Cr/Cu/Au, etc.
The method 70 may include removing any dielectric that covers the electrical connection pads of the top metal layer (step 88). The removal step 88 may include performing a conventional etch under the control of another photoresist mask.
The order of steps 86 and 88 may be inverted in other embodiments of methods of fabricating hermetic packages in which electrical feedthroughs have buried portions.
The method 70 may include mounting the micro-electronic structure that is to be packaged, e.g., micro-electronic structure 14. The micro-electronic structure is mounted inside the sealing ring on the semiconductor substrate (step 90). The mounting step may be, e.g., performed as described in above step 56.
In alternate embodiments, the step of mounting of the micro-electronic structure on the semiconductor substrate is performed at an earlier stage in the packaging method.
In other alternate embodiments, the micro-electronic structure is incorporated into the semiconductor substrate.
The method 70 includes bonding connection pads of the micro-electronic structure to the connection pads of the electrical feedthroughs, i.e., the connection pads of the top metal layer (step 92). The step 92 may involve performing wire bonding or flip-chip bonding as already described with respect to step 58 of
The method 70 includes positioning the housing over the sealing ring and sealing the housing to the substrate with a top joint material to complete the package's hermetic sealing joint, e.g., the sealing joint 18′ (step 94). In step 94, the top joint material may be a solder whose composition is compatible with the materials of the housing and the sealing ring. If both the housing and sealing ring are metallic, the top joint material may be a conventional metal-alloy solder, e.g., a solder comprising a lead, tin, and/or antimony alloy. The step 94 of sealing may be performed under a vacuum or under a non-reactive atmosphere, e.g., an argon or nitrogen atmosphere, as desired.
From the disclosure, drawings, and claims, other embodiments of the invention will be apparent to those skilled in the art.
