BACKGROUND OF THE INVENTION
Technical Field
The present invention is generally directed to the field of packaged integrated circuit devices, and, more particularly, to a novel build-up-package for integrated circuit devices and methods of making same.
Description of the Related Art
Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
So-called build-up-packaging (BUP) is a commonly employed technique for packaging integrated circuit devices. In general, build-up-packaging involves forming a mold compound material adjacent the sides of an integrated circuit die. Typically, this is accomplished by placing a plurality of singulated die on a section of tape, with the active side of the integrated circuit die being in contact with the tape. Thereafter, mold compound material is formed in the regions between and around the plurality of die. Typically, the mold compound may take the shape of a generally circular wafer. The thickness of the mold compound is approximately the same as that of the die that are subjected to the molding process. Eventually, after subsequent processing, the packaged die are singulated by cutting the mold material to achieve the desired package size.
FIGS. 1A-1B are, respectively, a cross-sectional side view and a plan view of an illustrative integrated circuit device packaged using the build-up technique described above. The packaged integrated circuit 10 is comprised of an integrated circuit die 12, a molded body 14, a first insulating layer 16, e.g., polyimide, a layer 18 of conductive lines or traces, and a second insulating layer 20. A schematically depicted bond pad 15 is formed on the active surface 13 of the die 12. The bond pad 15 is conductively coupled to the conductive layer 18, which may sometimes be referred to as a redistribution layer. A ball pad 22 and conductive ball 24 are conductively coupled to the conductive layer 18. In FIG. 1B, the first and second insulating layers 16, 20 are not shown for purposes of clarity. Of course, it is to be understood that FIGS. 1A-1B are schematic in nature and not intended to provide every detail associated with such prior art devices.
One problem associated with integrated circuit devices packaged using such build-up techniques is there is a tendency for the conductive lines or traces that are part of the conductive layer 18 to fail or crack at or near the interface 26 between the body of the die 12 and the molded body 14 in the area indicated by the dashed-line circle in FIG. 1B. Obviously, such defects may be detrimental and perhaps fatal to the operation of the packaged integrated circuit device 10.
BRIEF DESCRIPTION OF THE DRAWINGS
The present subject matter may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
FIGS. 1A-1B schematically depict an illustrative integrated circuit device packaged using a build-up technique;
FIGS. 2A-2F schematically depict an illustrative process flow for making a novel packaged integrated circuit device, as disclosed herein; and
FIGS. 3A-3I schematically depict another illustrative process flow for making a novel packaged integrated circuit device, as disclosed herein.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTION OF THE INVENTION
Illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. Although various regions and structures shown in the drawings are depicted as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and doped regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the subject matter disclosed herein.
FIGS. 2A-2F schematically depict one illustrative process flow for manufacturing the novel packaged integrated circuit devices disclosed herein. As shown in FIG. 2A, a layer of material 42 is formed above an active face 41 of an integrated circuit die 40. The die 40 has a plurality of bond pads 43, only one of which is depicted in FIG. 2A. The die 40 may be of any shape or thickness and it may be any type of integrated circuit device, e.g., a memory device, a logic device, an application specific integrated circuit device, etc. Thus, the present disclosure should not be considered as limited to any particular type of integrated circuit device. The bond pad 43 is schematic in nature as it is intended to represent any arrangement or configuration of bond pads that may be formed on the active surface 43 of the die 40. Similarly, the layer 42 may be comprised of a variety of materials and it may be formed using a variety of techniques. In one illustrative embodiment, the layer of material 42 is a layer of insulating material, e.g., polyimide, having a thickness of approximately 5-30 μm. The layer 42 may be formed by performing a variety of known techniques, e.g., spin-coating followed by curing, deposition, etc. Thus, the present subject matter should not be considered as limited to any particular material or method of manufacture for the layer 42.
Next, as shown in FIG. 2B, a masking layer 46 is formed above the layer 42 and an etching process, as indicated by the arrows 48, is performed to remove the portions of the layer 42 that are not covered by the masking layer 46. However, the width 50 need not be uniform around the entire perimeter of the die 40 in all applications. In one illustrative example, the width 50 of the removed portion may be approximately 100-500 μm. The masking layer 46 may be comprised of any material that is capable of performing the masking function, e.g., photoresist. The etching process 48 may be performed using traditional equipment and recipes to remove the exposed portions of the layer 42. After the etching process 48 is completed, the masking layer 46 may be removed.
Next, as shown in FIG. 2C, the structure is placed face down on a section of tape 51 and a molded body 44 is formed around the die 40 using traditional compression molding techniques. The tape 51 is removed in FIG. 2D. Although only a single die 40 is depicted in FIG. 2C, those skilled in the art will understand that, typically, the molded body 44 may be formed around a plurality of individual die 40 that are coupled to the tape 51. The molded body 44 may have an overall circular configuration, much like a semiconductor wafer, with a plurality of die 40 embedded therein. The molded body 44 may be made using a variety of known compression molding techniques, materials and equipment. In one illustrative embodiment, the molded body 44 is comprised of mold compound or encapsulant material that is commonly employed in encapsulating integrated circuit die. Note that the molded body 44 has a thickness that approximately corresponds to the combined thickness of the die 40 and the layer 42. As shown in FIGS. 2C and 2D, a portion or lip 53 of the molded body 44 extends above the corner 52 of the integrated circuit die 40. Stated another way, the portion 53 of the molded body 44 is positioned above the portions of the active face 41 of the die 40 that is not covered by the etched layer 42. The portions or extensions 53 of the molded body 44 extend inward beyond the primary vertical interface 61 between the die 40 and the molded body 44. In general, the compound molding process is continued until such time as the lips 53 of the molded body 44 engage or abut the reduced width layer 42 at the interface 55.
Thereafter, traditional processing techniques and structures may be employed to further complete the packaged integrated circuit device, as reflected in FIG. 2E. More specifically, such processing may involve formation of first and second insulating layers 58 and 60, and the formation of the conductive layer 18 using techniques known to those skilled in the art. Additionally, a ball pad 62 and ball 64 may be formed and conductively coupled to the conductive layer 18 using known techniques and materials. The conductive components may be made of a variety of materials, e.g., copper, aluminum, gold, etc.
FIG. 2F is a schematically depicted plan view of the resulting packaged die (without the insulating layers above the layer 42 depicted). As shown therein, the extensions 53 of the molded body 44 extend inwardly above the active face 41 of the die 40 beyond the primary vertical interface 61 between the die 40 and the molded body 44. Stated another way, the extensions 53 define a window 65 that has a footprint or size that is less than the footprint or size of the active face 41 of the underlying die 40. Accordingly, the conductive traces tend to experience less stress in the region indicated by the dashed-line circle 59 as compared to prior art BUP packaged devices, like the illustrative package depicted in FIGS. 1A-1B.
FIGS. 3A-3I depict another illustrative embodiment of a novel packaged integrated circuit device disclosed herein. In FIG. 3A, a plurality of singulated die 40 are attached to a section of tape 70. The active face 43 of the die 40 engages the tape 70.
Next, as shown in FIG. 3B, a CTE (coefficient of thermal expansion) buffer material 72 is formed around at least a portion of the perimeter of each of the die 40. In the illustrative example depicted in FIG. 3B, the CTE buffer material 72 is positioned around the entire perimeter of the die 40, although that is not required in all configurations. In general, the CTE buffer material 72 may have a coefficient of thermal expansion that is intermediate the coefficient of thermal expansion for the die 40 and the coefficient of thermal expansion for the molded body 44 that is to be formed adjacent the die 40. The CTE buffer material 72 may be comprised of a variety of different materials and it may be formed using a variety of techniques. In one illustrative example, the CTE buffer material 72 is a material that may be dispensed as a liquid or liquid-like material and thereafter cured. The size of the CTE buffer material 72 may also vary depending upon the particular application. In some cases, the CTE buffer material 72 may have an approximately triangular shaped cross-sectional configuration (as shown in FIG. 3B), with a leg length equal to approximately one-half the thickness of the die 40. In the illustrative example where the die 40 has a thickness of approximately 300-500 μm, the leg length of the CTE buffer material 72 may be approximately 150-250 μm. In one particularly illustrative embodiment, the CTE buffer material 72 may be comprised of traditional underfill material, or other liquid encapsulant material, having a coefficient of thermal expansion of approximately 4.14 ppm/° C. As an example, the die 40 may have a coefficient of thermal expansion of approximately 2.69 ppm/° C. while the molded body 44 may have a coefficient of thermal expansion of approximately 8.28 ppm/° C.
Next, as shown in FIG. 3C, the molded body 44 is formed around the plurality of singulated die 40 using known compressed molded techniques. Thereafter, the tape 70 is removed, as shown in FIG. 3D. Then, as shown in FIG. 3E, if desired, a grinding process may be performed to remove excess amounts of the molded body 44 from above the back surface 45 of the die 40. Of course, this grinding process need not be performed in all applications. After the grinding process is completed, another portion of tape 74 is attached to the back of the die 40/molded body 44. Next, as shown in FIG. 3G, traditional fabrication techniques are employed to form the necessary insulation layers, conductive layers and conductive balls 64, as described previously. Thereafter, as shown in FIG. 3H, the packaged die are singulated using traditional techniques.
FIG. 3I is a plan view depicting the packaged die (without the insulating materials present). As shown in this particular example, the CTE buffer material 72 essentially rings the perimeter of the die 40. Stated another way, in one illustrative embodiment, the CTE buffer material 72 is positioned between the die 40 and the molded body 44, at least at the substantially coplanar upper surfaces of the die 40, CTE buffer material 72 and molded body 44. In some cases, the CTE buffer material 72 may only be positioned along the side surfaces of the die 40 where the conductive traces will cross. The presence of the CTE buffer material 72, with its intermediate coefficient of thermal expansion, tends to reduce the localized stresses seen by the conductive traces in at least the region indicated by dashed lines 75.
Patent Grant
12315769
