This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-193386, filed on Jul. 28, 2008, the entire contents of which are incorporated herein by reference.
1. Field
The present invention relates to a buildup printed circuit board including an insulation layer.
2. Description of Related Art
A buildup printed circuit board is widely known as a printed circuit board (PCB) of multilayer structure. The buildup printed circuit board includes conductive wiring layers and resinous insulation layers which are stacked in sequence. Through holes are formed in the insulation layers. The through holes are filled with conductive material to create vias. Vias allow the electrical connection of the conductive wiring layers on opposite sides of the insulation layer. For example, silica as a filler of low thermal expansion is incorporated in the insulation layers such that the thermal expansion coefficient of the insulation layers is accommodated to that of the conductive wiring layers (see, for example, Japanese Laid-open Patent Publication No. 2005-268517).
A semiconductor chip, for example, is mounted on the front surface of the buildup printed circuit board with a solder bump. The solder bump is sandwiched between a conductive pad on the buildup printed circuit board and the corresponding conductive pad of the semiconductor chip. However, a sufficient rigidity is not ensured by the resinous insulation layer in which the filler such as silica is incorporated. Since the conductive wiring layer of copper and the insulation layer are stacked in sequence despite a different thermal expansion rate, the buildup printed circuit board may be deformed at a soldering temperature unless the rigidity of the insulation layer is sufficiently ensured. As a result, the solder joint between the buildup printed circuit board and the semiconductor chip may be poorly formed.
According to an aspect of the present invention, a buildup printed circuit board includes a first insulation layer that is formed of a resin material into which fiber cloth is embedded, and a second insulation layer that is formed of a resin material. The second insulation layer is stacked on a front surface of the first insulation layer on which a heating process has been performed. A conductive land is formed on a front surface of the second insulation layers, and a via which is provided in a through hole penetrates through the first insulation layer and the second insulation layer. The through hole is filled with a conductive material, and the via is connected to the conductive land.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are not restricted to the invention, as claimed.
The above and other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments in conjunction with the accompanying drawings, wherein:
Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
The conductive wiring layer 13 includes a conductive pattern 14 which extends on the insulation layer 12. Likewise, the conductive wiring layer 13 includes conductive lands 15 which can be formed on the front surface of the insulation layer 12. The conductive pattern 14 is connected to the conductive lands 15. The conductive lands 15 between which the insulation layer 12 is sandwiched are electrically connected by a via 16. In forming the via 16, a through hole is formed between the conductive lands 15 in the insulation layer 12. The through hole is filled up with a conductive material. The conductive wiring layer 13 and the via 16 can be formed from a conductive material such as Cu (copper).
A plurality of conductive pads 17 can be exposed to the front surface of the buildup printed circuit board 11. The conductive pad 17 is connected to the conductive land 15. The conductive pads 17 are formed with a conductive material, for example, Cu (copper). An overcoat layer 18 is stacked on the regions of the front surface of the buildup printed circuit board 11 except the conductive pads 17. A resin material, for example, is employed for the overcoat layer 18. The conductive pad 17 at the front surface of the buildup printed circuit board 11 is electrically connected to the conductive wiring layer 13 at the rear surface of this buildup printed circuit board 11.
Next, a method for manufacturing the buildup printed circuit board 11 will be described.
Then, an electroless deposition is performed on the front surface of the laminated body 34 to create a seed layer 36 of conductive material. The seed layer 36 extends into the through hole 35. Thereafter, as depicted in
After the removal of the photoresist 37, another first resin sheet 31 is stacked on the front surface of the laminated body 34. The conductive wiring layer 13 is sandwiched in between the laminated body 34 and the first resin sheet 31. The first resin sheet 31 is subjected to a heating process, and it is further stuck on the front surface of the laminated body 34. As mentioned above, the shape of the first resin sheet 31 conforms to that of the conductive wiring layer 13. Thereafter, the stacking and heating process of the second resin sheet 33, the formation of the through hole 35, the electroless plating, the deposition of the photoresist 37, the electrolytic plating, and the removal of the photoresist 37 are similarly repeated. In this way, the insulation layers 12 and the conductive wiring layers 13 in prescribed numbers of stacked layers are formed. The uppermost layer of the laminated body 34 is provided with conductive pads 17 and the overcoat layer 18. In this way, the manufacture of the buildup printed circuit board 11 is completed.
According to an embodiment of the buildup printed circuit board 11, the glass fiber cloth 23 is embedded in the insulation layer 12. As a result, the thermal expansion coefficient of the insulation layer 12 is suppressed to be low. The thermal expansion coefficient of the insulation layer 12 is accommodated to that of the conductive wiring layer 13, whereby the occurrence of a stress within the buildup printed circuit board 11 may be suppressed. Moreover, the rigidity of the insulation layer 12 is heightened due to the glass fiber cloth 23. Thus, even when a device such as a semiconductor chip is mounted on the front surface of the buildup printed circuit board 11, the rigidity of the joint between the buildup printed circuit board 11 and the device may be reliably ensured.
As a comparative example, in a case where the glass fiber cloth 23 is adjacently embedded to the front surface of the insulation layer 12, the glass fiber cloth may be exposed with respect to the insulation layer 12. On this occasion, when a plating solution for the seed layer 36 flows into the through hole 35, the plating solution may soak into the insulation layer 12 along the interface between the resin material and the fibers of the glass fiber cloth. Due to this, the via 16 may be connected, through the plating solution, to the conductive wiring layer 13 which is formed on the front surface of the second resin sheet 33. As a result, the via 16 may be electrically connected to the conductive pattern 14, and an abnormality can occur in the conductive pattern. Such a buildup printed circuit board would be unusable.
According to the foregoing embodiment, the plating solution flows into the through hole 35 when the seed layer 36 is formed. When the glass fiber cloth is exposed into the through hole 35, the plating solution may also soak into the first resin sheet 31 along the interface between the resin material and the fibers of the glass fiber cloth. However, according to an embodiment of the buildup printed circuit board 11, the second resin sheet 33 can be stacked on the first resin sheet 31. As a result, the glass fiber cloth may be reliably prevented from being exposed from the front surface of the insulation layer 12, that is, the front surface of the second resin sheet 33. Accordingly, even if the plating solution soaks along the interface between the resin material and the fibers, the plating solution may be prevented from reaching the front surface of the second resin sheet 33. Consequently, the via 16 may be prevented from being electrically connected to the conductive pattern 14.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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2008-193386 | Jul 2008 | JP | national |