BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1A is a schematic diagram showing a conventional chip package structure;
FIG. 1B is a schematic top view illustrating the conventional chip package structure shown in FIG. 1A;
FIG. 2 is a schematic top view illustrating another conventional chip package structure;
FIG. 3A is a schematic diagram showing a chip package structure according to a first embodiment of the present invention;
FIG. 3B is a schematic top view illustrating the chip package structure shown in FIG. 3A;
FIG. 3C is a schematic diagram showing the structure of the first boding wires shown in FIG. 3A;
FIG. 4 is a schematic top view illustrating a chip package structure according to a second embodiment of the present invention; and
FIG. 5 is a schematic top view illustrating a chip package structure according to a third embodiment of the present invention.