Patent Application
20080029865
So-called “embedded dielectric” technologies, in which one or ever a plurality of semiconductor chips and, if appropriate, further components are surrounded with a plastic housing by techniques such as introduction by molding, introduction by lamination or layer-by-layer construction of the plastic, have numerous advantages over conventional technologies in which the semiconductor chip is applied to a substrate by means of contacts such as solder balls and is subsequently surrounded with a plastic housing.
Thus, they permit for example smaller and lighter devices and enable the fixed connection of a plurality of chips in a single housing and also a higher density of electrical connections.
Moreover, the “embedded dielectric” technologies afford advantages during production. A semiconductor device is known, for the production of which semiconductor chips are processed to form a composite plate or a panel by introduction into a plastic composition by molding, wherein the active top sides of the semiconductor chips form a coplanar area with the top side of the composite plate, while their edges and the rear side are covered by the plastic housing composition. A wiring structure having conductor tracks separated from one another by dielectric layers can be applied comparatively simply to the coplanar area, which affords a planar surface for process steps such as photolithography steps.
What is problematic in this case, however, is that warpage of the composite plate that are caused by different coefficients of thermal expansion of semiconductor material and plastic housing composition destroy the planarity of the surface. During the application of the rewiring structure, this results in losses in the accuracy with which structures such as contact areas and conductor tracks can be applied. Consequently, only a limited density of electrical connections is possible.
An electric device is produced as described herein and includes a wiring structure with particularly high accuracy on the surface of an integrated circuit chip using “embedded dielectric technology”. A carrier wafer is provided comprising a semiconductor material. A wiring structure with conductor tracks and contact pads is applied to a top side of the carrier wafer, thereby providing a plurality of semiconductor device positions arranged in rows and columns. Subsequently, integrated circuit chips are applied in the semiconductor device positions and embedded into a plastic housing composition, thereby forming a composite plate including the integrated circuit chips and the plastic housing composition. After curing the plastic housing composition, the carrier wafer is removed.
The above and still further features and advantages of the electronic device and method will become apparent upon consideration of the following definition, description and descriptive figures of specific embodiments thereof, wherein like reference numerals in the various figures are utilized to designate like components. While these descriptions go into specific details of the invention, it should be understood that variations may and do exist and would be apparent to those skilled in the art based on the descriptions herein.
Exemplary embodiments are explained in more detail below with reference to the accompanying figures, where:
Identical parts are provided with the same reference symbols in all of the figures.
As described herein, rewiring structures can be applied with particularly high accuracy. An exemplary method for producing an electronic device (e.g., semiconductor device), as described herein, includes providing a carrier wafer comprising a semiconductor material having a top side and an underside. A typical wiring structure including at least one rewiring layer with metallic conductor tracks and contact pads is applied to the top side of the carrier wafer, wherein device positions arranged in tows and columns are provided. The entire wiring structure can immediately be tested in the wafer assemblage as required. As a result, defective device positions can already be identified at a very early stage of production and, if appropriate, be marked and not populated with an integrated circuit chip (e.g., semiconductor chip). After the application and, if appropriate, also the testing of the wiring structure, semiconductor chips are applied to the top side—provided with the wiring structure—of the carrier wafer in the device positions. It is also possible to provide a plurality of integrated circuit chips for the formation of a multichip module or else further components per device position.
After the application and fixing of the chips in the device positions, a plastic housing composition is applied to the top side of the carrier wafer and embeds the integrated circuit chips into the housing composition, thereby forming a composite plate comprising integrated circuit chips and plastic housing composition. After the curing of the housing composition, the composite plate is stable and self-supporting, such that the carrier wafer can be removed and the wiring structure remains of the composite plate.
Warped areas are not suitable for the application of wiring structures having particularly high density therefore requiring a particularly high accuracy. On the other hand, however, warpage of the composite plate can only be minimized with comparatively high outlay and cannot be completely suppressed. Therefore, the wiring structure should not be applied directly to the composite plate, abut rather first to a carrier wafer. A carrier wafer composed of metal would be conceivable, in principle, but is disadvantageous owing to its high production costs. The necessary removal of the carrier wafer would also have to be carried out completely via etching in the case of a metallic carrier wafer and would therefore by very time-consuming and costly. Moreover, many adhesives used for fixing the semiconductor chips, for example, exhibit only inadequate adhesion on metallic surfaces.
With a carrier wafer comprising a semiconductor material, however, these problems can be solved since a semiconductor wafer would not have to be produced separately as a carrier wafer. Rather, wafers constituting rejects from semiconductor chip production, for example, could be used as a carrier wafer. Semiconductor wafers can be patterned very well and simply via proven processes, which results in a high density of the structures produced, In addition, semiconductor wafers can be removed very simply, rapidly and cost-effectively by thinning via grind and/or etching, the risk of inadvertent damage to the wiring structure being particularly how due to the differing etchability of the carrier wafer and the wiring structure. Since the carrier wafer comprises a single material, warpage during the production process in negligible.
The semiconductor chips typically have an active top side with integrated circuits and contact areas and a passive rear side. In one embodiment, the semiconductor chips are mounted by their active top side onto the contact pads on the top side of the carrier wafer using flip-chip technology. For this purpose, the contact pads can be reinforced galvanically or in electroless fashion, or be provided with solder balls, prior to the application of the semiconductor chips.
In an alternate embodiment, the semiconductor chips can also be mounted by their rear sides onto the top side of the carrier wafer. In this case, contact areas on their active top side are electrically connected to the contact pads on the carrier wafer via bonding wires.
The semiconductor chips can be connected to the wiring structure on the carrier wafer via a soldering process. Alternatively, it is also possible for the semiconductor chips to be connected to the wiring structure on the carrier wafer via adhesive bonding, alloying or thermocompression welding.
The plastic housing composition embeds the semiconductor chips in such a way that the latter, if appropriate apart from the side connected to the wiring structure, are completely enclosed by the plastic housing composition. For this purpose, the plastic housing composition can be applied to the semiconductor chips and to the carrier wafer via compression molding or else via spin-on methods or jet printing methods.
Once the plastic housing composition has cured, it forms together with the semiconductor chips a self-supporting composite plate. After the application of the plastic housing composition, therefore, a composite body composed of the carrier wafer and the composite plate having the semiconductor chips embedded into the plastic housing composition has formed, wherein the composite plate is arranged on the top side—provided with the wiring structure—of the carrier wafer in such a way that the semiconductor chips embedded into the plastic housing composition are applied in the device positions.
After the curing of the plastic housing composition, the carrier wafer can be removed, for example, by thinning via grinding or etching or via a combination of both. This is particularly simple because the semiconductor material of the carrier wafer can be machined comparatively easily via standard processes. The composite plate remains, and its side formerly facing the carrier wafer is a coplanar area composed of surfaces of the (semiconductor chips arranged in the device positions, comprising plastic housing composition and including the wiring structure with conductor tracks, contact pads and, if appropriate, a dielectric. Thus, the metallization with which the semiconductor chip is now provided is uncovered during the removal of the carrier wafer. Contact pads of the metallization can either be used directly as external contacts if the semiconductor devices are those having so-called leadless packages. However, the uncovered contact pads can also be reinforced galvanically or in electroless fashion, or be provided with solder balls.
The composite plate is typically singulated into semiconductor devices via a sawing process, for example, after the removal of the carrier wafer. However, it is also possible, for example, if the individual semiconductor devices are intended to have additional stability for further processing or for transport, to singulate the composite plate into semiconductor devices prior to the removal of the carrier wafer.
The method provides a number of advantages, including the feature of being carried out simply and at the wafer level in front end processes and are therefore highly cost-effective. Via the carrier wafer comprising a semiconductor material with at most minimal warpage, the method enables a very high accuracy in applying the rewiring structure, the accuracy being limited practically only by the accuracy with which the semiconductor chips are deposited during placement. As a result, with the method, it is possible on the one hand to achieve very high device densities on a single semiconductor wafer, and on the other hand semiconductor devices with a particularly high density of metallic structures such as connections, for example, can be produced with comparatively low outlay.
Exemplary embodiments are described in greater detail below with reference to the figures.
The wiring structure 5 is produced by customary process such as photolithography and deposition of metals. The wiring structure 5 may include, for example, contact pads and conductor tracks and also a plurality of wiring layers. Only the contact pads are indicated schematically in the figure, for the sake of clarity. Since the carrier wafer 1 in principle comprises a single material, e.g., a semiconductor material, and does not constitute a composite of materials having different coefficients of thermal expansion, it experiences only negligible warpage in the event of temperature fluctuations occurring during different process steps. The wiring structure 5 can therefore be applied to its top side 4 with particularly high accuracy and therefore also with particularly high density.
As shown in
After the curing of the plastic housing composition 10, the composite plate 16 is self-supporting and so stable that the carrier wafer 1 can be removed. This is done, for example, by grinding away and/or etching the carrier wafer 1 is illustrated in
A second embodiment of the method is illustrated in
As shown in
As illustrated in
When the carrier wafer 1 is subsequently removed, as shown in
While the invention has been described in detail with reference to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2006 027 283.8 | Jun 2006 | DE | national |
This application claims priority under 35 U.S.C. §119 to Application No. DE 102006027283.8 filed on Jun. 9, 2006, entitled “Method for Producing a Semiconductor Device,” the entire contents of which are hereby incorporated by reference.
