ELECTRONIC DEVICE

BACKGROUND
1. Field of the Disclosure

The present disclosure relates to an electronic device, in particular to an electronic device including an electronic component bonded to a package structure.

2. Description of the Related Art

A solder joint may be utilized to bond different components, such as an electronic component and a package structure. However, when the size of an electronic device is reduced. It is difficult to control the amount of solder material. Therefore, a solder cracking and/or solder bridging may occur, which reduces the manufacturing yield for an electronic device. In order to provide the desired enhancement in performance, a new electronic device is required.

SUMMARY

In some embodiments, an electronic device includes a package structure and a power regulating element. The package structure includes an electronic component, a plurality of first conductive structures, and an encapsulant. The plurality of first conductive structures are connected to the electronic component. The encapsulant encapsulates the electronic component and exposes a portion of the plurality of first conductive structures. The power regulating component includes a plurality of second conductive structures directly bonded with the plurality of first conductive structures and configured to provide the electronic component with a power signal.

In some embodiments, an electronic device includes a package structure and an integrated circuit. The package structure includes an encapsulant, an electronic component, and a first conductive element. The electronic component is encapsulated by the encapsulant. The first conductive element is exposed by the encapsulant. The integrated circuit includes a second conductive element connected to the first conductive element through a non-solder joint.

In some embodiments, an electronic device includes a package structure and a second electronic component. The package structure includes an electronic component, a first conductive structure, and a second conductive structure. The first conductive structure is disposed over the electronic component. The second conductive structure is disposed adjacent to a lateral surface of the electronic component. The second electronic component includes a plurality of third conductive structures directly connected to the first conductive structure and the second conductive structure.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 2 illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 3A illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 3B illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 4A illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 4B illustrates a layout of an electronic device according to some embodiments of the present disclosure.

FIG. 4C illustrates a cross-sectional view of an example of an electronic device according to some embodiments of the present disclosure.

FIG. 5A is a partial enlarged view of an electronic device according to some embodiments of the present disclosure.

FIG. 5B is a partial enlarged view of an electronic device according to some embodiments of the present disclosure.

FIG. 5C is a partial enlarged view of an electronic device according to some embodiments of the present disclosure.

FIG. 6 is a partial enlarged view of an electronic device according to some embodiments of the present disclosure.

FIG. 7A illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7B illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7C illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7D illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7E illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7F illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7G illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7H illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7I illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 7J illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 8A illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 8B illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 8C illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

FIG. 8D illustrates one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

The following disclosure provides many different arrangements, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described as follows. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation or disposal of a first feature over or on a second feature in the description that follows may include arrangements in which the first and second features are formed or disposed in direct contact, and may also include arrangements in which one or more additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. The same reference numerals and/or letters refer to the same or similar parts. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various arrangements and/or configurations.

Arrangements of the present disclosure are discussed in detail as follows. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific arrangements discussed are merely illustrative and do not limit the scope of the disclosure.

FIG. 1 illustrates a cross-sectional view of an example of an electronic device 1a according to some embodiments of the present disclosure. In some embodiments, the electronic device 1a may include a carrier 10, a package structure 20, a bonding structure 30, and an electronic component 40.

In some embodiments, the carrier 10 (or a circuit structure) may include a circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The carrier 10 may include at least one dielectric layer and a redistribution structure, trace, and/or circuit within the dielectric layer. In some embodiments, the carrier 10 may be electrically connected to a power source (not shown), and the carrier 10 may be included in a transmission path for providing an electronic component(s) or a device with power. In some embodiments, conductive terminals (not shown) may be disposed on or disposed under the lower surface (not annotated) of the carrier 10, which may be configured to electrically connect to an external device.

Electrical connections 11 may be disposed on or disposed over an upper surface (not annotated) of the carrier 10. The electrical connection 11 may include, for example, a conductive pad, a solder element, and/or other suitable elements. The conductive pad may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. The solder element may include alloys of gold and tin solder or alloys of silver and tin solder, or other suitable materials.

The package structure 20 may be disposed on or disposed over the upper surface of the carrier 10. In some embodiments, the package structure 20 may include an electronic component 21, electrical connections 22, conductive elements 23a, 23b, 23d, and 24, as well as an encapsulant 25.

The electronic component 21 may be a chip or a die including a semiconductor substrate, one or more integrated circuit (IC) devices and one or more overlying interconnection structures therein. The IC devices may include active devices such as transistors and/or passive devices such as resistors, capacitors, inductors, or a combination thereof. For example, the electronic component 21 may include a system on chip (SoC). For example, the electronic component 21 may include an application-specific IC (ASIC), a radio frequency integrated circuit (RFIC), a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a field-programmable gate array (FPGA), or another type of IC. The electronic component 21 may have a surface 21s1 and a surface 21s2 opposite to the surface 21s1. The surface 21s1 of the electronic component 21 may face the carrier 10. The surface 21s1 may function as an active surface, and the surface 21s2 may function as a backside surface. In some embodiments, signal may be transmitted from the electronic component 21 to an external device through the surface 21s1. In some embodiments, at least a portion of power may be transmitted to the electronic component 21 through the surface 21s2.

The electronic component 21 may be electrically connected to the carrier 10 by the electrical connection 22 and the electrical connection 11. The electrical connection 22 may be disposed on or disposed under the surface 21s1 of the electronic component 21. The electrical connection 22 may include, for example, a conductive pad or other suitable elements. The electrical connection 22 may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials.

In some embodiments, the electronic component 21 may include a redistribution structure 21r, which extends to the surface 21s2 of the electronic component 21. In some embodiments, the redistribution structure 21r may be configured to transmit power to the IC(s) of the electronic component 21. In some embodiments, the redistribution structure 21r may be configured to transmit heat to the outside. The redistribution structure 21r may include at least one conductive trace, and/or conductive via embedded within a dielectric layer(s) or the semiconductor substrate (e.g., a silicon substrate) of the electronic component 21.

In some embodiments, the electronic component 21 may include a redistribution circuit 21t, a logic circuit 21c, and a power delivery circuit 21p. The redistribution circuit 21t is disposed adjacent to the surface 21s1. The power delivery circuit 21p is disposed adjacent to the surface 21s2. The power delivery circuit 21p may include the redistribution structure 21r. The logic circuit 21c may receive a power (or a power signal) through the power delivery circuit 21p.

The conductive elements 23a, 23b, and 23d may be disposed on or disposed over the surface 21s2 of the electronic component 21. The conductive elements 23a, 23b, and 23d may be electrically connected to the electronic component 21. Each of the conductive elements 23a, 23b, and 23d may include a conductive pillar, conductive via, or other suitable components. In some embodiments, the conductive element 23a may be configured to provide a path for transmitting power. In some embodiments, the conductive element 23b may provide a path connected to ground. For example, a grounding signal may be transmitted by the conductive element 23b. The conductive elements 23a and 23b may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials.

The conductive element 24 may extend from the upper surface of the carrier 10. The conductive element 24 may be disposed at or adjacent to the side (or a lateral side surface) of the electronic component 21. In some embodiments, the conductive element 24 may penetrate or fully penetrate the encapsulant 25. The conductive element 24 may include a conductive pillar (e.g., power pillar), conductive via, or other suitable components. In some embodiments, the conductive element 24 may be configured to provide a path for transmitting power from the carrier 10. The conductive element 24 may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. A surface 24s1 (or a top surface) of the conductive element 24 may be substantially aligned with a surface 23s1 (or a top surface) of the conductive element 23a (or 23b).

The encapsulant 25 may be disposed on or disposed over the carrier 10. In some embodiments, the encapsulant 25 may encapsulate the electronic component 21, the conductive elements 23a and 23b, and the conductive element 24. The encapsulant 25 may include insulation or dielectric material. For example, the encapsulant 25 may include a molding compound. In some embodiments, the encapsulant 25 may be made of molding material that may include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or other another suitable encapsulant. Suitable fillers may also be included, such as powdered SiO₂. The encapsulant 25 may have a surface 25s1 (or an upper surface) far away from the carrier 10. In some embodiments, the surface 25s1 of the encapsulant 25 may be substantially aligned with the upper surface of the conductive element 23a (or 23b). In some embodiments, the surface 25s1 of the encapsulant 25 may be substantially aligned with the upper surface of the conductive element 24.

In some embodiments, the bonding structure 30 (or a hybrid-bond structure) may be disposed on or disposed over the upper surface of the package structure 20. In some embodiments, the bonding structure 30 may be disposed on or disposed over the surface 25s1 of the encapsulant 25. The bonding structure 30 may be formed by a non-solder bonding technique, for example, a hybrid-bond technique. For example, the non-solder bonding technique may involve a bonding between metal (or alloy) materials (such as Cu to Cu bonding) and a bonding between dielectric materials (such as oxide to oxide bonding). In some embodiments, the bonding structure 30 may include pads 31a, 31b, 31c, and 31d, a dielectric layer 32, pads 33a, 33b, 33c, and 33d, and a dielectric layer 34. In some embodiments, the bonding structure 30 has no solder materials, such as tin or its derivatives.

The pads 31a, 31b, 31c, and 31d (or conductive elements) may be disposed within the dielectric layer 32 and located at the same level. The pads 31a, 31b, 31c, and 31d may be disposed on or disposed over the surface 25s1 of the encapsulant 25. The pads 31a, 31b, and 31d may protrude from the conductive elements 23a, 23b, and 23d. The pads 31a to 31d may be exposed by the encapsulant 25. The pad 31a may be electrically connected to the conductive element 23a. The pad 31b may be electrically connected to the conductive element 23b. The pad 31c may be electrically connected to the conductive element 24. The pad 31d may be electrically connected to the conductive element 23d. The pads 31a, 31b, 31c, and 31d may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the surface area of the pad 31a may be less than the surface area of the conductive element 23a. In other embodiments, the surface area of the pad 31a may be equal to the surface area of the conductive element 23a. In some embodiments, the surface area of the pad 31c may be less than the surface area of the conductive element 24. In other embodiments, the surface area of the pad 31c may be equal to the surface area of the conductive element 24.

The dielectric layer 32 (or a connection layer) may be disposed on or disposed over the package structure 20. The dielectric layer 32 may be disposed on or disposed over the surface 25s1 of the encapsulant 25. In some embodiments, the dielectric layer 32 may include an organic material, such as polyimide or other suitable materials. In some embodiments, the dielectric layer 32 may include an inorganic material, such as oxide, nitride, oxynitride, or other suitable materials.

The pads 33a, 33b, 33c, and 33d (or conductive elements) may be disposed within the dielectric layer 34 and located at the same level. The pads 33a, 33b, 33c, and 33d may be disposed on or disposed over the pads 31a, 31b, 31c, and 31d, respectively. The pad 33a may be electrically connected to the pad 31a. The pad 33b may be electrically connected to the pad 31b. The pad 33c may be electrically connected to the pad 31c. The material of the pads 33a, 33b, 33c, and 33d may be the same as or similar to that of the pad 31a. In some embodiments, the pad 31a (or 31b or 31c or 31d) may be substantially aligned with the pad 33a (or 33b or 33c or 33d). That is, the bonded surface of the pad 31a may be substantially completely bonded with that of the pad 33a. Each of the conductive element 23a, 23b, 23d, pads 31a to 31d, 33a-33d, or a combination thereof may be regarded as a conductive structure, and the conductive element 23a, 23b, 23d, pads 31a to 31d, 33a-33d, or a combination thereof may be regarded as a portion of said conductive structure.

The dielectric layer 34 (or a connection layer) may be disposed on or disposed over the dielectric layer 32. The material of the dielectric layer 34 may be the same as or similar to that of the dielectric layer 32. In some embodiments, a portion of the upper surface (not annotated) of the dielectric layer 32 may be exposed by the dielectric layer 34.

In some embodiments, the pads 31a and 33a may be regarded as an integral pad, as there is no boundary or a nonobvious boundary between the pads 31a and 33a. In some embodiments, the pads 31b and 33b may be regarded as an integral pad, as there is no boundary or a nonobvious boundary between the pads 31b and 33b. In some embodiments, the pads 31c and 33c may be regarded as an integral pad, as there is no boundary or a nonobvious boundary between the pads 31c and 33c. In some embodiments, there is no boundary or a nonobvious boundary between the dielectric layers 32 and 34.

In some embodiments, the electronic component 40 (or a power regulating component) may be disposed on or disposed over the bonding structure 30. The electronic component 40 may be configured to regulate power, such as a voltage and/or a current. The electronic component 40 may include a power regulating element, such as a voltage regulating element. The electronic component 40 may include a surface 40s1 (or a lower surface) and a surface 40s2 (or an upper surface) opposite to the surface 40s1. The surface 40s1 may face the package structure 20. Regulated power may be transmitted to the electronic component 21 through the surface 40s1 of the electronic component 40. A portion of the dielectric layer is not covered by the electronic component 40.

As shown in FIG. 1, a path P1 may indicate a transmission path of an electrical signal, such as power. In some embodiments, power may be transmitted from the carrier 10 to the electronic component 40 through the conductive element 24, the pads 31c and 33c, and the electronic component 40 as shown by the path P1. A path P2 may indicate a transmission path of an electrical signal, such as power. In some embodiments, power may be transmitted from the electronic component 40 to the electronic component 21 through the pads 33a and 31a, and the conductive element 23a as shown by the path P1. A path P3 may indicate a transmission path of an electrical signal which is electrically connected to the ground. For example, a grounding signal may be transmitted by the pads 31b and 33b. In some embodiments, electrical signal may be transmitted from the electronic component 40 to the pads 31b and 33b. In this embodiment, power may be transmitted through the backside surface (e.g., surface 21s2) of the electronic component 21. As a result, more signal input/output (I/O) terminals may be disposed over the surface 21s1 of the electronic component 21, which allows more signals (e.g., data signal) to be processed, input, and/or output.

In a comparative example, an electronic component is bonded to a package structure through a solder joint, which involves a reflow process configured to assist a solder material (e.g., tin or alloy including tin) to reach its eutectic temperature so that the solder material undergoes a phase change to a liquid or molten state. When the amount of the solder material is insufficient, a solder cracking may occur and cause an electrical disconnection between the electronic component and the package structure. Conversely, when the amount of the solder material is more than necessary, a solder bridging may occur and cause an electrical short. Further, it is a challenge to control the amount of the solder material as the size of an electronic device is reduced. In the embodiments of the present disclosure, the electronic component 40 may be bonded to the package structure 20 through a non-solder joint. More specifically, a hybrid-bond technique or a metal to metal bonding (e.g., copper to copper bonding) is utilized to bond the package structure 20 and the electronic component 40. In some embodiments, the pads 33a, 33b, 33c, and 33d are provided or formed on the surface 40s1 of the electronic component 40 and bonded to the pads 31a, 31b, 31c, and 31d through a hybrid-bond technique, which is performed at a temperature equal to or less than 200° C. Since the electronic component 40 and the package structure 20 are bonded by a non-solder joint, the aforesaid problems caused by using solder materials may be prevented. In some embodiments, when a reflow process is performed to joint other components, the pads 31a, 31b, 31c, 33a, 33b, and 33c are not reflowed. That is, each of the melting points of the pads 31a, 31b, 31c, 33a, 33b, and 33c is higher or greater than a temperature of a reflow process, such as 280° C., 270° C., 260° C., or fewer.

FIG. 2 illustrates a cross-sectional view of an example of an electronic device 1b according to some embodiments of the present disclosure. The electronic device 1b is similar to the electronic device 1a as shown in FIG. 1, and the differences therebetween are described below.

In some embodiments, the electronic device 1b may further include a conductive element 23c, a pad 35a, and a pad 35b. The conductive element 23c may be disposed on or disposed over the surface 21s2 of the electronic component 21. The conductive element 23c may be disposed within the encapsulant 25. The conductive element 23c may be connected to the pad 35b. In some embodiments, the conductive element 23c may be configured to transmit heat, emitted from the electronic component 21, to the outside of the package structure 20.

The pad 35a may be disposed on or disposed over the surface 25s1 of the encapsulant 25. The pad 35a may be disposed within the dielectric layer 32. The pad 35a may be configured to transmit heat, from the package structure 20, to the outside. The pad 35b may be disposed on or disposed over the surface 25s1 of the encapsulant 25. The pad 35b may be disposed within the dielectric layer 32. In some embodiments, the upper surface (not annotated) of the pad 35b may be exposed from the dielectric layer 32 or exposed to the air. The pad 35b may be connected to the conductive element 23c. The pad 35b may be configured to transmit heat, emitted from the electronic component 21, to the outside. In some embodiments, each of the pads 35a and 35b may function as a dummy pad, which is electrically isolated from the electronic component 40. In some embodiments, the pads 35a (or 35b) may be electrically isolated from the electronic component 21. The pad 35b is not covered by the electronic component 40. Each of the conductive element 23c, pads 35a and 35b may also be referred to as a heat dissipating structure. The pads 31a, 31b, and 31d may be interposed or disposed between the pads 35a and 35b. A path P4 may indicate a transmission path of heat. In some embodiments, heat may be transmitted from the electronic component 21 to the outside through the pad 35a (or 35b) as shown by the path P4. In some embodiments, a heat dissipating element (not shown), such as a heat sink, may be disposed over or connected to the pad 35b. which thereby facilitates the heat dissipation of the electronic device 1b.

In some embodiments, the conductive element 23a, conductive element 23b, and/or conductive element 24 may collectively function as a reinforcement structure 50. The reinforcement structure 50 may be disposed between the electronic component 40 and the electronic component 21. The reinforcement structure 50 may be configured to reduce a warpage of the electronic component 21, which enables the pads 31a, 31b, 31c, and 31d to be bonded and/or at least partially aligned with the pads 33a, 33b, 33c, and 33d, respectively. In some embodiments, the reinforcement structure 50 may include pads 35a and 35b. In some embodiments, the reinforcement structure 50 may have a thickness T1, which is defined by the conductive element 23a, and a thickness T2, which is defined by the conductive element 23c and the pad 35b, and which is different from the thickness T1.

FIG. 3A illustrates a cross-sectional view of an example of an electronic device 1c according to some embodiments of the present disclosure. The electronic device 1c is similar to the electronic device 1a as shown in FIG. 1, and the differences therebetween are described below.

In some embodiments, the pad 31a may be at least partially misaligned with the pad 33a. In some embodiments, the pad 31b may be at least partially misaligned with the pad 33b. In some embodiments, the pad 31c may be at least partially misaligned with the pad 33c. A central axis 31r of the pad 31d (or 31a or 31b or 31c) may be misaligned with a central axis 33r of the pad 33d (or 33a or 33b or 33c). In some embodiments, a portion of the bonded surface of the pad 31a may be exposed from the pad 33a. In some embodiments, a portion of the bonded surface of the pad 31a may be in contact with the dielectric layer 34. In some embodiments, a lateral surface 34s1 (or a left side) of the dielectric layer 34 may be coplanar with a lateral surface 32s1 (or a left side) of the dielectric layer 32.

FIG. 3B illustrates a cross-sectional view of an example of an electronic device 1c′ according to some embodiments of the present disclosure. The electronic device 1c′ is similar to the electronic device 1c as shown in FIG. 3A, and the differences therebetween are described below. In some embodiments, the lateral surface 34s1 of the dielectric layer 34 may be misaligned with the lateral surface 32s1 of the dielectric layer 32. In this embodiment, the lateral surface 34s1 of the dielectric layer 34, the lateral surface 32s1 and the top surface (not annotated) of the dielectric layer 32 may define a stepped structure.

FIG. 4A illustrates a cross-sectional view of an example of an electronic device 1d according to some embodiments of the present disclosure. The electronic device 1d is similar to the electronic device 1a as shown in FIG. 1, and the differences therebetween are described below.

In some embodiments, the electronic device 1d may further include a conductive pattern 60. In some embodiments, the conductive pattern 60 may be disposed on or disposed over the package structure 20. In some embodiments, the conductive pattern 60 may be disposed on or disposed over the surface 25s1 of the encapsulant 25. In some embodiments, the conductive pattern 60 may abut, contact, and/or surround the bottom (not annotated) of the pads 31a, 31b, and/or 31c. In some embodiments, the conductive pattern 60 may include a conductive material(s), such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the conductive pattern 60 may define multiple openings. In some embodiments, the conductive pattern 60 may be configured to transmit heat or function as a part of a heat dissipating element. The conductive pattern 60 may be configured to increase the paths or areas for heat dissipating.

FIG. 4B illustrates a layout of an electronic device 1e according to some embodiments of the present disclosure. As shown in FIG. 4B, the conductive pattern 60 may include conductive portions 61, a conductive portion 62, and openings 63 and 64. The conductive portion 61 may be separated from the conductive portion 62 by the opening 63. The conductive portion 61 may be disposed between the openings 63 and 64. In some embodiments, each of pads 31, which may be the same as or similar to the pads 31a, 31b, 31c, and 31d, may penetrate the conductive portion 61. In some embodiments, each of the pads 31 may contact the conductive portion 61. The pad 31 may pass through the opening 64 defined by the conductive portion 61. In some embodiments, the conductive portion 61 may include a ring-shaped profile. The encapsulant 25 may be exposed by the opening 63. The opening 64 may have a circular profile, an elliptical profile, or other suitable profiles.

Refer back to FIG. 4A, the conductive portions 61 may be connected to the pads 31a, 31b, and 31d, which thereby decreases the impedance of the power delivery path. The conductive portions 61 may be configured to adjust the impedance of the power delivery path, and enhance the efficiency of the power transmission.

FIG. 4C illustrates a cross-sectional view of an example of an electronic device 1d′ according to some embodiments of the present disclosure. The electronic device 1d′ is similar to the electronic device 1d as shown in FIG. 4A, and the differences therebetween are described below. In some embodiments, the pads 31a, 31b, 31c, and 31d may be disposed over the conductive portions 61 of the conductive pattern 60. The conductive portions 61 may include parts 61a, 61b, and 61c separated from each other. The pads 31a to 31c may be disposed on or over the parts 61a to 61c.

FIG. 5A is a partial enlarged view of an electronic device, such as the electronic device 1a as shown in FIG. 1, according to some embodiments of the present disclosure. In some embodiments, the pad 31 may be tapered along a direction far away from a pad 33, which may be the same as or similar to the pads 33a, 33b, 33c, and 33d. In some embodiments, the pad 33 may be tapered along a direction far away from the pad 31.

FIG. 5B is a partial enlarged view of an electronic device, such as the electronic device 1a as shown in FIG. 1, according to some embodiments of the present disclosure. In some embodiments, the pad 33 may have a substantially straight sidewall, which is substantially perpendicular to the upper surface (not annotated) of the dielectric layer 34. In some embodiments, the sidewall of the pad 33 may include a rough surface, which is formed due to a dry etching technique configured to remove the dielectric layer 34.

FIG. 5C is a partial enlarged view of an electronic device, such as the electronic device 1a as shown in FIG. 1, according to some embodiments of the present disclosure. In some embodiments, the pad 31 may have a substantially straight sidewall, which is substantially perpendicular to the lower surface (not annotated) of the dielectric layer 32. In some embodiments, the sidewall of the pad 31 may include a rough surface, which is formed due to a dry etching technique configured to remove the dielectric layer 32.

FIG. 6 is a partial enlarged view of an electronic device, such as the electronic device 1a as shown in FIG. 1, according to some embodiments of the present disclosure. In some embodiments, the conductive element 23 may have an extending portion 231 abutting the surface 25s1 of the encapsulant 25. In some embodiments, the conductive element 24 may have an extending portion 241 abutting the surface 25s1 of the encapsulant 25. The extending portions 231 and 241 may be formed due to a grinding technique performed on the conductive element 23, the conductive element 24, and the encapsulant 25. In some embodiments, the extending portion 231 may be protruded so that the boundary of the conductive element 23 may be discontinuous at the saddle point of the extending portion 231 from a top view.

FIG. 7A to FIG. 7J illustrate various stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

Referring to FIG. 7A, a carrier 10 may be provided. A plurality of electrical connections 11 may be formed on the upper surface of the carrier 10.

Referring to FIG. 7B, a conductive element 24 may be formed on the upper surface of the carrier 10.

Referring to FIG. 7C, an electronic component 21 may be provided. A plurality of electrical connections 22 may be formed on a surface 21s1 of the electronic component 21. Conductive elements 23a and 23b may be formed on a surface 21s2 of the electronic component 21. The electronic component 21 may be bonded to or attached to the carrier 10 by bonding the electrical connections 22 and 11.

Referring to FIG. 7D, an encapsulant 25 may be formed on the upper surface of the carrier 10. The encapsulant 25 may encapsulate the electronic component 21, and conductive element 23a, 23b and 24.

Referring to FIG. 7E, a grinding technique may be performed on a surface 25s1 of the encapsulant 25. As a result, the surface 25s1 of the encapsulant 25 may be substantially aligned with the upper surfaces (not annotated) of the conductive elements 23a, 23b, and 24. Further, the extending portions (not shown) of the conductive elements 23a, 23b, and 24 may be formed adjacent to the surface 25s1 of the encapsulant 25. As a result, a package structure 20 may be produced.

Referring to FIG. 7F, a dielectric layer 32 may be formed on the surface 25s1 of the encapsulant 25. A plurality of openings 320 may be formed by, for example, an etching technique. The conductive elements 23a, 23b, and 24 may be exposed from the openings 320.

Referring to FIG. 7G, a metallization layer 31′ may be formed on the dielectric layer 32 and fill the openings 320.

Referring to FIG. 7H, a polishing technique may be performed to remove the excessive portion of the metallization layer 31′ that is located over the upper surface of the dielectric layer 32. As a result, pads 31a, 31b, 31c, and 31d may be formed. It should be noted that the stages as shown in FIG. 7A to FIG. 7H illustrate a structure formed on a wafer, panel, or strip. That is, there are repeated units, each of which includes a corresponding package structure 20, connected to each other by the wafer, panel, or strip, and the structure as shown in FIG. 7A to FIG. 7H is one of the plurality of repeated units.

Referring to FIG. 7I, an electronic component 40 may be provided. Pads 33a, 33b, 33c, and 33d as well as a dielectric layer 34 may be formed on or under a surface 40s1 of the electronic component 40. The electronic component 40 is a singulated unit. In this stage, multiple electronic components 40 may be mounted on or attached to a wafer structure (or a panel or a strip) which includes the carrier 10 and the package structure 20.

Referring to FIG. 7J, the electronic component 40 may be bonded or attached to the package structure 20. Further, the plurality of repeated units on a wafer (or a panel or a strip) may be sawed, diced, or divided. As a result, an electronic device may be produced, such as the electronic device 1a as shown in FIG. 1. In some embodiments, a non-solder bonding technique, such as a hybrid-bond technique, may be performed to bond the package structure 20 and the electronic component 40. The pads 31a, 31b, 31c, and 31d may be bonded to the pads 33a, 33b, 33c, and 33d, respectively. The dielectric layer 32 may be bonded to the dielectric layer 34. At this stage, no solder material is utilized or reflowed. In this embodiment, a hybrid-bond technique is utilized, and therefore the issue of solder cracking and/or solder bridging may be prevented, which facilitates miniaturization of the electronic device 1a.

FIG. 8A to FIG. 8D illustrate various stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. The initial stage of the illustrated process is the same as, or similar to, the stage illustrated in FIG. 7A through FIG. 7E. FIG. 8A depicts a stage subsequent to that depicted in FIG. 7E.

Referring to FIG. 8A, a metallization layer 60′ may be formed on the surface 25s1 of the encapsulant 25.

Referring to FIG. 8B, the metallization layer 60′ may be patterned to form the conductive pattern 60 that defines multiple openings.

Referring to FIG. 8C, the dielectric layer 32 may be formed on or formed over the conductive pattern 60. A plurality of the openings 320 may be formed.

Referring to FIG. 8D, the pads 31a, 31b, 31c, and 31d may be formed on or formed over the dielectric layer 32. The electronic component 40 may be attached to the package structure 20. As a result, an electronic device, such as the electronic device 1d as shown in FIG. 4A, may be produced.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of arrangements of this disclosure are not deviated from by such an arrangement.

As used herein the term “active surface” may refer to a surface of an electronic component or passive element on which contact terminals such as contact pads are disposed or a surface through which a signal passes.

As used herein, the term “vertical” is used to refer to upward and downward directions, whereas the term “horizontal” refers to directions transverse to the vertical directions.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm. A surface can be deemed to be substantially flat if a displacement between the highest point and the lowest point of the surface does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.

As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity exceeding approximately 10⁴S/m, such as at least 10⁵S/m or at least 10⁶S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific arrangements thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other arrangements of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit, and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

ELECTRONIC DEVICE

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